Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: To prevent deterioration of light incident/emission environment in a semiconductor device in which a transmissive material is laminated on an optical element forming surface via an adhesive. The semiconductor device includes a semiconductor element manufactured by chip size packaging, a transmissive material which is bonded with an adhesive to cover an optical element forming surface of the semiconductor element, and a side surface protective resin which covers an entire side surface where a layer structure of the semiconductor element and the transmissive material is exposed.

Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

Abstract: There is provided an imaging device capable of further improving image quality of a subject, particularly a lesion portion such as cancer. There is provided an imaging device including: a first substrate including a first pixel array unit in which a plurality of pixels having at least a first photoelectric conversion unit is arranged in a two-dimensional manner, a first wiring layer, and a first support layer stacked in this order; and a second substrate including a second pixel array unit in which a plurality of pixels having at least a second photoelectric conversion unit is arranged in a two-dimensional manner, a second wiring layer, and a second support layer stacked in this order, in which the first support layer and the second support layer are bonded to each other to form a stacked structure, and at least one of the support layers includes an antireflection layer.

Abstract: A power semiconductor device includes first and second disc-shaped electrodes and a wafer sandwiched between the electrodes. An outer insulating ring is attached to the first and second electrodes and surrounds the wafer. An inner insulating ring is located inside of the outer insulating ring and surrounds the wafer and a ring-shaped first flange portion laterally surrounds a main portion of the first electrode. An O-ring radially surrounds the main portion of the first electrode and is sandwiched in a vertical direction between the inner insulating ring and the first flange portion. In a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

Abstract: A solid-state image sensor is provided that includes a semiconductor substrate, a charge accumulator disposed in the semiconductor substrate and configured to accumulate charge, a photoelectric converter provided above the semiconductor substrate and configured to convert light to charge, and a through electrode passing through the semiconductor substrate and electrically connecting the charge accumulator with the photoelectric converter. At an end portion on the photoelectric converter side of the through electrode, a cross-sectional area of a conductor positioned at the center of the through electrode in a cut section orthogonal to a through direction of the through electrode gradually increases toward the photoelectric converter along the through direction.

Abstract: A semiconductor package is disclosed for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip, a housing lid and thermal-conductive liquid. A chip is disposed on the substrate layer and electrically coupled to the substrate layer. The chip includes at least one through silicon via (TSV). The housing lid is disposed above both the substrate layer and the chip. Also, the housing lid is coupled to the substrate layer at its edge for forming an internal space that encompasses the chip. The thermal-conductive liquid is filled within the internal space.

Abstract: A semiconductor module assembly includes a cooling body having a cooling body main body and a cooling body attachment with a channel structure for a heat-transporting fluid. The channel structure is hermetically sealed with a cooling body main body surface so that the cooling body attachment and the cooling body main body are in direct contact with the heat-transporting fluid. The cooling body attachment includes a central piece having essentially parallel channels of the channel structure, and end pieces arranged on both sides of the central piece. Each end piece has deflection channels of the channel structure, which are arranged to establish a fluidic connection between the essentially parallel channels of the central piece. A semiconductor module contacts the cooling body, with the hermetically sealed channel structure of the cooling body attachment and the heat-transporting fluid forming a pulsating heat pipe which is thermally conductively connected to the semiconductor module.

Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

Abstract: An electronic device is provided. The electronic device includes an electronic component and a heat dissipation structure. The electronic component has a passive surface and a plurality of conductive vias exposed from the passive surface. The heat dissipation structure is disposed on the passive surface and configured to transmit a plurality of independent powers to the conductive vias through the passive surface.

Abstract: An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

Abstract: A first frame is supported by a heat sink plate, surrounds an unmounted region of the heat sink plate, contains a resin, and has a first surface. A second frame contains a resin, and has a second surface opposing the first surface. An external terminal electrode passes between the first surface and the second surface. An adhesive layer contains a resin, and includes a lower portion, an upper portion, and an intermediate portion. The lower portion connects the external terminal electrode and the first surface to each other. The upper portion connects the external terminal electrode and the second surface to each other. The intermediate portion is disposed within a through hole of the external terminal electrode, and connects the lower portion and the upper portion to each other.

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

Abstract: A miniaturized and high-power semiconductor package device with its own heat-dissipating ability includes a thermal conductor, a redistribution layer, an electronic device, a molding layer, and a solder ball. The redistribution layer includes a first surface defining an opening, a second surface opposite to the first surface, and a circuit layer. The thermal conductor is disposed in the opening. The electronic device is disposed on the first surface of the redistribution layer above the thermal conductor. The molding layer is formed on the first surface and surrounding the electronic device. The solder balls are disposed on the second surface of the redistribution layer and can form electrical connections to the circuit layer.

Abstract: This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

Abstract: An electronic package is provided. The electronic package includes a power regulating component, an electronic component, and a circuit structure. The circuit structure separates the power regulating component and the electronic component. The circuit structure is configured to provide a first power to the power regulating component. The power regulating component is configured to provide a second power to the electronic component through the circuit structure.

Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device.

Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.