Patents Examined by Peter Bradford
  • Patent number: 10559662
    Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Hong He, Juntao Li
  • Patent number: 10553658
    Abstract: Disclosed are an encapsulation unit which may prevent deterioration of thin film transistors so as to improve reliability and an organic light emitting display device including the same. At least one transparent oxide film is disposed under at least one of a plurality of inorganic encapsulation films disposed on a light emitting element and, thus, oxygen in the at least one transparent oxide film combines with hydrogen introduced during formation of the inorganic encapsulation films to prevent hydrogen from diffusing into the thin film transistors.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 4, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Young Oh
  • Patent number: 10553502
    Abstract: A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 4, 2020
    Assignee: VEECO PRECISION SURFACE PROCESSING LLC
    Inventors: Laura Mauer, John Taddei, John Clark, Elena Lawrence, Eric Kurt Zwirnmann, David A. Goldberg, Jonathan Yutkowitz
  • Patent number: 10546754
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10546915
    Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
  • Patent number: 10546780
    Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Subhashish Mukherjee, Raja Selvaraj, Venugopal Gopinathan
  • Patent number: 10541240
    Abstract: The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 21, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Okagaki
  • Patent number: 10535794
    Abstract: A method for manufacturing a light emitting device includes placing a light emitting element on a releasable base material so that a first face of the light emitting element is in contact with the releasable base material. An entire area of the first face is a first area. A wavelength converting material is provided on the releasable base material to cover an entirety of the light emitting element. The releasable base material is removed. A first electrically conductive material covers the first electrode and the wavelength converting material. An entire area of the first electrically conductive material viewed in a height direction is a second area larger than the first area. A second electrically conductive material covers the second electrode and the wavelength converting material. An entire area of the second electrically conductive material viewed in the height direction is a third area larger than the first area.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 14, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Masafumi Kuramoto, Daisuke Iwakura
  • Patent number: 10536219
    Abstract: Disclosed are structures and methods for a monolithic silicon (Si) coherent transceiver with integrated laser and gain elements wherein an InP chip is bonded to the Si chip in a recess formed in that Si chip.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 14, 2020
    Assignee: Acacia Communications, Inc.
    Inventors: Christopher Doerr, Long Chen
  • Patent number: 10535556
    Abstract: A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh, Pei-Wen Huang
  • Patent number: 10522636
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack disposed over a first portion of a substrate and a fin channel material disposed over a second portion of the substrate, patterning the nanosheet stack disposed over the first portion of the substrate to form two or more nanosheet channels for at least one nanosheet field-effect transistor, patterning the fin channel material disposed over the second portion of the substrate to form one or more fins for at least one fin field-effect transistor, forming a first dielectric layer surrounding the nanosheet channels and the one or more fins, patterning a mask layer over the one or more fins, removing the first dielectric layer surrounding the nanosheet channels, removing the mask layer, forming a second dielectric layer surrounding the nanosheet channels and over the first dielectric layer surrounding the one or more fins, and forming a gate conductive layer over the second dielectric layer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, Chen Zhang, Peng Xu, Huiming Bu, Kangguo Cheng
  • Patent number: 10515882
    Abstract: A package for a semiconductor device includes: a plate-shaped base member having a substantially rectangular shape in a plan view; a first and second electrode solder pads configured to be electrically connected to a semiconductor element when the semiconductor element is mounted on an upper surface of the base member, the electrode solder pads being disposed at a lower surface side of the base member to face each other in a first direction; and first and second auxiliary solder pads disposed on a lower surface of the base member, the auxiliary solder pads being disposed at both sides of the electrode solder pads such that the first and second electrode solder pads are disposed between the first and second auxiliary solder pads in a plan view.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 24, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Satoshi Kataoka
  • Patent number: 10516098
    Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 24, 2019
    Assignee: Purdue Research Foundation
    Inventors: Shehrin Sayed, Vinh Quang Diep, Kerem Y Camsari, Supriyo Datta
  • Patent number: 10515884
    Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Li-Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10510853
    Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
  • Patent number: 10510539
    Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Chun-Lung Ni, Jr-Jung Lin, Chih-Han Lin
  • Patent number: 10510798
    Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ming Lu, Chih-Hui Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Chih-Chang Huang, Ching-Ho Hsu
  • Patent number: 10497817
    Abstract: P-N diodes that include p-type doped diamond and devices, such as p-n-p heterojunction bipolar transistors, that incorporate the p-n diodes are provided. In the p-n diodes, the diamond at the p-n junction has a positive electron affinity and is passivated by a thin layer of inorganic material that provides a tunneling layer that passivates the bonding interface states, without hindering carrier transport across the interface.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 3, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventor: Zhenqiang Ma
  • Patent number: 10468459
    Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: November 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Oda, Michiaki Sano
  • Patent number: 10461279
    Abstract: The present disclosure relates to a flat panel display device and a top organic light emitting diode (Top-OLED). The Top-OLED includes: a light emitting unit and a light output coupling unit configured on a light output surface of the light emitting unit, wherein the light output coupling unit is configured with a first light emitting coupling layer and a second first light emitting coupling layer configured on the light output surface of the light emitting unit in sequence A refractive index of the first light emitting coupling layer is greater than a refractive index of the second light emitting coupling layer. The light emitting coupling layers configured on the light output surface of the light emitting unit having the refractive index being configured to be decreased gradually, so as to enhance the external quantum efficiency and to increase the amount of outputting light beams.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 29, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventor: Wei Yuan