Patents Examined by Peter Bradford
  • Patent number: 10297667
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack disposed over a first portion of a substrate and a fin channel material disposed over a second portion of the substrate, patterning the nanosheet stack disposed over the first portion of the substrate to form two or more nanosheet channels for at least one nanosheet field-effect transistor, patterning the fin channel material disposed over the second portion of the substrate to form one or more fins for at least one fin field-effect transistor, forming a first dielectric layer surrounding the nanosheet channels and the one or more fins, patterning a mask layer over the one or more fins, removing the first dielectric layer surrounding the nanosheet channels, removing the mask layer, forming a second dielectric layer surrounding the nanosheet channels and over the first dielectric layer surrounding the one or more fins, and forming a gate conductive layer over the second dielectric layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, Chen Zhang, Peng Xu, Huiming Bu, Kangguo Cheng
  • Patent number: 10284300
    Abstract: Disclosed are structures and methods for a monolithic silicon (Si) coherent transceiver with integrated laser and gain elements wherein an InP chip is bonded to the Si chip in a recess formed in that Si chip.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 7, 2019
    Assignee: Acacia Communications, Inc.
    Inventors: Christopher Doerr, Long Chen
  • Patent number: 10273794
    Abstract: Apparatus, systems, and methods for ranging operate to use a wireline active ranging system to initially determine a relative distance and relative direction from a first well (e.g., ranging well) to a second well (e.g., target well) and an EM azimuthal logging tool to maintain or adjust the distance from the target well while drilling the ranging well. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 30, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Hsu-Hsiang Wu, Burkay Donderici
  • Patent number: 10270059
    Abstract: A flexible display and manufacturing method thereof are disclosed. In one aspect, the flexible display includes a flexible substrate including a bending area, an insulating layer disposed on the flexible substrate, and at least one groove in the insulating layer within the bending area. The flexible display also includes a stress relaxation layer disposed on the at least one groove and a plurality of wires formed over the insulating layer and the stress relaxation layer.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nam Jin Kim
  • Patent number: 10263212
    Abstract: Provided is an organic light emitting display device in which a plurality of pixel areas each including an emitting area and a non-emitting area is defined in a display area. The organic light emitting display device includes: an auxiliary electrode in a part of a non-emitting area of at least one pixel area; an auxiliary electrode contact portion formed as a part of the auxiliary electrode; a first electrode in the emitting areas of the plurality of pixel areas; an organic layer on the first electrode and the auxiliary electrode; and a second electrode on the organic layer. The auxiliary electrode contact portion electrically connects the auxiliary electrode and the second electrode. A distance from a center of the auxiliary electrode contact portion to a terminal end of the first electrode in the emitting area may be 3 ?m or more.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Junho Lee
  • Patent number: 10262222
    Abstract: The invention relates to a method for measuring dimensions of a target object. The method comprises acquiring depth data representative of the physical space, the depth data comprising data of the target object, converting the depth data into a point cloud, extracting at least one plane from the point cloud, identifying a ground plane, eliminating the ground plane from the point cloud, extracting at least one point cluster from the remaining point cloud, identifying a point cluster of the target object, estimating dimensions of the target object based on the point cluster of the target object.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 16, 2019
    Assignee: SICK INC.
    Inventors: Alexander Shteinfeld, Richard Lydon, George Liu, Udrekh Gavale
  • Patent number: 10249725
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a gate metal layer, a via, a first source metal layer, a drain metal layer, and a second source metal layer. The source electrode, the drain electrode, and the gate electrode are present on the active layer. The first insulating layer is present on the source electrode, the drain electrode, and the gate electrode. The gate metal layer, the first source metal layer, the second source metal layer, and the drain metal layer are present on the first insulating layer. The gate metal layer includes a narrow portion and a wider portion. The via is present between the metal gate layer and the gate electrode. The second source metal layer is present between the gate metal layer and the drain metal layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang
  • Patent number: 10230049
    Abstract: Provided herein are perovskite-polymer films, methods of forming polymer-perovskite films, and devices including polymer-perovskite films. The polymer-perovskite films may include a plurality of methylammonium lead chloride (CH3NH3PbCl3) nanopillar crystals embedded in a polymer matrix. The devices can be optoelectronic devices, such as light emitting diodes, which include polymer-perovskite films. The polymer-perovskite films of the devices can be hole transport layers in the devices. The methods of making films may include spin casting a precursor solution followed by thermal annealing.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 12, 2019
    Assignee: Florida State University Research Foundation, Inc.
    Inventors: Biwu Ma, Hanwei Gao, Yu Tian, Yichuan Ling
  • Patent number: 10194522
    Abstract: A method comprises applying an adhesive to a first substrate and a second substrate to secure the first substrate to the second substrate. The adhesive extends in a plane on one side of an interposer that also extends in the plane, and is contiguous with the adhesive. The interposer comprises openings to enable flow of adhesive through the openings to form adhesive bond areas on one of the substrates where the areas substantially conform to the openings and lie adjacent to adhesive free areas. The adhesive substantially covers the other of the substrates so that the bond areas produce regions of reduced adhesive strength to the one substrate compared to the bond strength of the adhesive to the other substrate. Adjusting opening sizes adjusts area bond strengths. One substrate may comprise a VTM, the other a heat spreader, and the adhesive, a TIM. An article of manufacture comprises the substrate-adhesive-interposer-adhesive-substrate layers.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Michael Gaynes
  • Patent number: 10192944
    Abstract: An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Hyun Ju Kang, Sang Won Shin
  • Patent number: 10170711
    Abstract: A thin-film transistor layer, an organic light-emitting diode layer, and other layers may be used in forming an array of pixels on a substrate in a display. Vias may be formed through one or more layers of the display such as the substrate layer to form vertical signal paths. The vertical signal paths may convey signals between display driver circuitry underneath the display and the pixels. The vias may pass through a polymer layer and may contact pads formed within openings in the substrate. Vias may pass through a glass support layer. Metal traces may be formed in the thin-film transistor layer to create signal paths such as data lines and gate lines. Portions of the metal traces may form vias through a polymer layer such as a substrate layer or a polymer layer that has been formed on top of the substrate layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 1, 2019
    Assignee: Apple Inc.
    Inventors: Jason C. Sauers, Jean-Pierre S. Guillou, Peter J. Kardassakis, Shaowei Qin, Yi Tao
  • Patent number: 10163649
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10163641
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lee, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu, Hsin-Chi Chen
  • Patent number: 10163689
    Abstract: A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh, Pei-Wen Huang
  • Patent number: 10164104
    Abstract: A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Ruilong Xie
  • Patent number: 10164153
    Abstract: A light-emitting element includes: a semiconductor structure; light-reflecting electrodes; a first insulating film having: one or more first n-side openings and one or more first p-side openings; one or more interconnect electrodes on an upper surface of the first insulating film; a first electrode on the upper surface of the first insulating film; a second electrode on the upper surface of the first insulating film; a second insulating film having: one or more second n-side openings and one or more second p-side openings; a first external connection portion; and a second external connection portion.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 25, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Keiji Emura, Takamasa Sunda
  • Patent number: 10164031
    Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
  • Patent number: 10157991
    Abstract: A method for fabricating a memory device is provided. The method for fabricating a memory device includes forming a first dielectric layer over a substrate and forming a floating gate layer over the first dielectric layer. The method further includes forming a hard mask layer over the floating gate layer and etching the hard mask layer to form a recess in the hard mask layer. The method further includes patterning a portion of the hard mask layer under the recess to form a recessed feature having a first tip corner and etching the recessed feature and the floating gate layer to form a floating gate having a second tip corner. The method further includes depositing a second dielectric layer over the floating gate and forming a control gate partially over the floating gate and separating from the floating gate by the second dielectric layer.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Hsing-Chih Lin
  • Patent number: 10141418
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 27, 2018
    Assignee: STC.UNM
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 10141400
    Abstract: A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate, a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction, a gate spacer between the first gate electrode and the second gate electrode, and source/drain regions in the active region at opposite sides of the first gate electrode. The source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and, when viewed in a plan view, the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jaekyu Lee