Abstract: A computing device, method and computer program product are provided in order to develop a system model. In a method, a simulation model is designed that is configured to digitally simulate a corresponding portion of a system. The method also includes associating a simulation assessment module with the simulation model. The simulation assessment module is configured to verify one or more signals propagating within the simulation model. In an instance in which the simulation assessment module has verified the one or more signals, the method includes performing a unit test upon the simulation model to confirm proper operation of the simulation model. In an instance in which the unit test is successful, the method includes integrating a plurality of simulation models to form the system model.

Abstract: The present invention relates a modular charging system including a wall mounted outlet preserving charger and charging additional accessories, such as battery blocks, wireless device chargers, supporting chargers for wearable devices such as watches, and car chargers, each for use independently or in combination with electronic devices. The present invention typically includes a wall charger with one or more electrical outlets on the front face so that the use of the wall outlet is not lost. The wall charger of the present invention is suitable for use in any major country and may be adapted to the outlet configuration and voltage of those countries.

Abstract: Methods, systems and apparatus for approximating a target quantum state. In one aspect, a method for determining a target quantum state includes the actions of receiving data representing a target quantum state of a quantum system as a result of applying a quantum circuit to an initial quantum state of the quantum system; determining an approximate quantum circuit that approximates the specific quantum circuit by adaptively adjusting a number of T gates available to the specific quantum circuit; and applying the determined approximate quantum circuit to the initial quantum state to obtain an approximation of the target quantum state.

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Abstract: A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results, (ii) changes to the product since a previous estimation or regression test has been performed and (iii) information regarding a user. The method includes identifying a candidate test having a confidence score that is below a threshold, in response to the identification of the candidate test, performing the candidate test, and providing, to a user, results of the performing of the candidate test.

Abstract: A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.

Abstract: Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.

Abstract: A system includes a processor configured to determine a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the processor is configured to perform a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The power parameter includes at least one of a power density of a tile containing the cell, a voltage drop of the tile containing the cell, or a voltage drop of the cell.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

Abstract: A method including: obtaining an image of at least part of a substrate, wherein the image includes at least one feature of a device being manufactured in a layer on the substrate; obtaining a layout of features associated with a previous layer adjacent to the layer on the substrate; calculating one or more image-related metrics in dependence on: 1) a contour determined from the image including the at least one feature and 2) the layout; and determining one or more control parameters of a lithographic apparatus and/or one or more further processes in a manufacturing process of the device in dependence on the one or more image-related metrics, wherein at least one of the control parameters is determined to modify the geometry of the contour in order to improve the one or more image-related metrics.

Abstract: This application discloses a computing system implementing a power estimator can read in waveform data generated during functional verification of a circuit design describing an electronic device, detect toggles in the signals of the waveform data, correlate the detected toggles in the signals to arcs associated with logic gates in the circuit design, and track a number of times each of the arcs has been correlated to the detected toggles. After the waveform data has been read, the power estimator can look-up power values for each arc having been correlated to a detected signal toggle, multiple the power values by the tracked number of times each of the arcs been correlated to the detected toggles to compute power estimates, and generate an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.

Abstract: Methods and systems, including computer programs encoded on a computer storage medium. In one aspect, a method includes the actions of receiving a request to perform convolutional computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying the convolutional computation to be performed on a feature tensor and a filter and padding applied to the feature tensor prior to performing the convolutional computation; and generating instructions that when executed by the hardware circuit cause the hardware circuit to perform operations comprising: transferring feature tensor data from a main memory of the hardware circuit to a scratchpad memory of the hardware circuit; and repeatedly performing the following operations: identifying a current subset of the feature tensor; and determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory.

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

Abstract: A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.

Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: Computer-implemented systems and methods for automatically generating an electronic circuit IP block are provided. The disclosed systems and methods maintain the process design rules (DRC Clean), connectivity (LVS Clean) correctness, and obey Reliability Verification (RV) and DFM (Design for Manufacturability) constraints, including time constraints. Exemplary systems and methods may include an electronic circuit layout generator and/or IP generator to obtain manufacturing processes and design rules from an external source, define a type of electronic circuit to be fabricated, prepare a circuit schematic of the defined electronic circuit, and generate an IP block for the defined electronic circuit based on the circuit schematic. A computer program generator is provided to create the defined electronic circuit. A computer readable storage medium contains processing instructions for obtaining the manufacturing processes and design rules and for fabricating the electronic circuit.

Abstract: This application discloses a pooling processing method, applied to a pooling processing system of a convolutional neural network.