Patents Examined by Pho M. Luu
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Patent number: 11749358Abstract: A semiconductor integrated circuit includes a register, a first interface circuit, an oscillation circuit that generates a first clock, a pll circuit, a control circuit, and a second interface circuit. The register stores numerical information representing a data size. The first interface circuit receives, from a first device, a first timing signal for data transfer. Responding to receipt of the first timing signal, the control circuit inputs the first timing signal to the pll circuit and counts the number of toggles of the first timing signal. When a counted number of toggles of the first timing signal matches a value corresponding to the numerical information, the control circuit inputs the first clock to the pll circuit. The second interface circuit transmits, to a second device, the first timing signal or a second timing signal, which corresponds to a second clock generated based on the first clock by the pll circuit.Type: GrantFiled: June 15, 2021Date of Patent: September 5, 2023Assignee: Kioxia CorporationInventor: Tomoaki Suzuki
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Patent number: 11742022Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.Type: GrantFiled: December 2, 2021Date of Patent: August 29, 2023Assignee: Zeno Semiconductor Inc.Inventor: Yuniarto Widjaja
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Patent number: 11735231Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.Type: GrantFiled: November 15, 2021Date of Patent: August 22, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hyun Jeong, Jae-hyun Park
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Patent number: 11737283Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: August 22, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11729995Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: August 15, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11729991Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: August 15, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11729996Abstract: An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.Type: GrantFiled: July 30, 2021Date of Patent: August 15, 2023Assignee: International Business Machines CorporationInventors: Heng Wu, Ruilong Xie, Julien Frougier, Bruce B. Doris
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Patent number: 11723296Abstract: A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.Type: GrantFiled: May 1, 2020Date of Patent: August 8, 2023Assignee: U.S. Department of EnergyInventors: Kevin Brown, Thomas Roser
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Patent number: 11723208Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other inType: GrantFiled: March 15, 2022Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Patent number: 11723214Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.Type: GrantFiled: April 26, 2022Date of Patent: August 8, 2023Assignee: SK hynix Inc.Inventor: Hwang Yeon Kim
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Patent number: 11715529Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: March 8, 2022Date of Patent: August 1, 2023Assignee: KIOXIA CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
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Patent number: 11705202Abstract: A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.Type: GrantFiled: October 12, 2021Date of Patent: July 18, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhipeng Dong, Venkatagirish Nagavarapu, Haibo Li
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Patent number: 11694748Abstract: A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.Type: GrantFiled: April 8, 2022Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
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Patent number: 11694743Abstract: A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.Type: GrantFiled: June 6, 2021Date of Patent: July 4, 2023Assignee: Realtek Semiconductor Corp.Inventor: Ching-Sheng Cheng
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Patent number: 11696450Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: July 4, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11696451Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.Type: GrantFiled: November 1, 2021Date of Patent: July 4, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 11688471Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.Type: GrantFiled: March 8, 2022Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Hong-Yan Chen, Yingda Dong
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Patent number: 11688477Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.Type: GrantFiled: October 15, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
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Patent number: 11675500Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.Type: GrantFiled: February 5, 2021Date of Patent: June 13, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Youn Cheul Kim, Richard S. Chernicoff, Khandker Nazrul Quader, Robert D. Norman, Tianhong Yan, Sayeef Salahuddin, Eli Harari
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Patent number: 11670372Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.Type: GrantFiled: October 27, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Hong-Yan Chen, Yingda Dong