Patents Examined by Phuc T. Dang
  • Patent number: 10755994
    Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: You-Lung Yen
  • Patent number: 10756153
    Abstract: An organic light emitting display device is disclosed, which removes an inorganic film from a bending area and minimizes a crack of a routing line to enable an extreme bending. The organic light emitting display device comprises a substrate having a display area and a bending area; a display assembly provided on a display area of the substrate; a routing line arranged on the bending area of the substrate and connected to the display assembly; and an organic layer provided on the bending area of the substrate, covering the routing line, wherein the bending area of the substrate has only the routing line and the organic layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 25, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Eunah Kim
  • Patent number: 10748862
    Abstract: A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 10748874
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10745269
    Abstract: A package includes a support structure having an electrically insulating material, a microelectromechanical system (MEMS) component, a cover structure having an electrically insulating material and mounted on the support structure for at least partially covering the MEMS component, and an electronic component embedded in one of the support structure and the cover structure. At least one of the support structure and the cover structure has or provides an electrically conductive contact structure.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: August 18, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Nick Renaud-Bezot, Bernhard Reitmaier
  • Patent number: 10734483
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 4, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Makoto Mizukami, Masaru Furukawa, Teruyuki Ohashi
  • Patent number: 10734225
    Abstract: A nitride semiconductor substrate includes a sapphire substrate and a nitride semiconductor layer formed thereon and containing a group III element including Al and nitrogen as a main component. A surface of the sapphire substrate where the nitride semiconductor layer is formed includes recesses having a maximum opening size of from 2 nm to 60 nm in an amount of from 1×109 pieces to 1×1011 pieces per cm2. The recesses and surfaces immediately above the recesses form spaces. Of a surface of the nitride semiconductor layer on the sapphire substrate side, a height difference ?H between a surface immediately above of each recess and a surface in contact with a flat surface is 10 nm or less. A portion of the nitride semiconductor layer above each recess has a crystalline structure produced by growth along a polar plane of the group III element.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 4, 2020
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Akira Yoshikawa, Tomohiro Morishita, Motoaki Iwaya
  • Patent number: 10732474
    Abstract: A display apparatus includes a pixel connected to a data line. The pixel includes a first pixel electrode and a second pixel electrode spaced apart from the first pixel electrode in an extension direction of the data line. The second pixel electrode includes first to fourth stem portions. The third and fourth stem portions are further from the first pixel electrode than the first and second stem portions in the extension direction. The first and second stem portions are connected to one another to form a “V”-shaped structure. The third and fourth stem portions are connected to one another to form an inverted “V”-shaped structure.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sehyun Lee, Haksun Chang, Byoungsun Na, Seungmin Lee, Jaeho Choi
  • Patent number: 10727281
    Abstract: A display device includes a scan line extending in a first direction, a data line and a driving voltage line extending in a second direction crossing the first direction, a switching thin film transistor (“TFT”) connected to the scan line and the data line, a driving TFT connected to the switching TFT and including a driving semiconductor layer and a driving gate electrode, a storage capacitor connected to the driving TFT and including first and second storage capacitor plates, a node connection line between the data line and the driving voltage line and connected to the driving gate electrode, and a shielding portion between the data line and the node connection line.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junwon Choi, Yunkyeong In, Wonmi Hwang, Junyong An
  • Patent number: 10720411
    Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
  • Patent number: 10714536
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10714705
    Abstract: A display device may include a first substrate, a second substrate, a light emitting structure, a seal member, a seal structure, a pad electrode, and a connection wire. The second substrate may overlap the first substrate. The light emitting structure may be positioned between the first substrate and the second substrate. The seal member may be positioned between the first substrate and the second substrate. The seal structure may be spaced from the seal member. A section of the seal member may be positioned between the light emitting structure and the seal structure. The seal structure may be positioned between the seal member and the pad electrode. The connection wire may electrically connect the seal structure and the pad electrode.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Haegoo Jung, Hwan Woo Lee, Yeon-Shil Jung, Boock Jang
  • Patent number: 10707236
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a light-shielding pattern layer, a buffer layer, an active layer, a gate insulating layer and a gate electrode on a base substrate, which are away from the base substrate in sequence; depositing an amorphous silicon (a-Si) film on the base substrate in a temperature range of 15-150° C.; forming a first interlayer dielectric (ILD) at least disposed above the active layer by patterning the a-Si film; forming through holes in the first ILD, through which a source contact region and a drain contact region of the active layer are exposed; and forming a source electrode and a drain electrode on the first ILD, which are respectively connected with the source contact region and the drain contact region via the through holes.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang, Fengjuan Liu
  • Patent number: 10707039
    Abstract: The present invention generally relates to a mechanism for making the anchor of the MEMS switch more robust for current handling. The disclosure includes a modified leg and anchor design that allows for larger currents to be handled by the MEMS switch.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 7, 2020
    Assignee: Cavendish Kinetics, Inc.
    Inventors: Robertus Petrus Van Kampen, Richard L. Knipe
  • Patent number: 10703625
    Abstract: A MEMS apparatus with adjustable spring includes a central portion, a peripheral portion and at least one spring. The peripheral portion surrounds the central portion and is spaced apart from the central portion. The spring includes a peripheral section, an outward extension section and a central section. The peripheral section is connected to the outward extension section. An amount of thermal expansion per unit temperature change of the outward extension section is greater than that of the peripheral section or greater than that of the central section.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 7, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Nan Yeh, Yu-Wen Hsu, Chao-Ta Huang
  • Patent number: 10707144
    Abstract: A method of creating thermal boundaries in a substrate is provided. The method includes forming the substrate with first and second sections to be in direct thermal communication with first and second thermal elements, respectively, machining, in the substrate, first and second cavities for defining a third section of the substrate between the first and second sections and disposing a material having a characteristic thermal conductivity that is substantially less than that of the ceramic in the first and second cavities.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 7, 2020
    Assignee: RAYTHEON COMPANY
    Inventor: Thomas P. Sprafke
  • Patent number: 10707292
    Abstract: The organic light emitting display device according to the exemplary aspect of the present disclosure includes a flexible substrate which includes a first area, a second area, and a bending area between the first area and the second area, and a wiring line on the bending area of the flexible substrate. The wiring line has a plurality of unit patterns having a rhombic shape. In this case, each of plurality of unit patterns shares a part of one side with the adjacent unit pattern. According to the organic light emitting display device according to an exemplary aspect of the present disclosure, a wiring line having a new shape is disposed in the bending area so that a stress which is applied to the wiring line and the protective layer formed in the bending area may be minimized.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: SeYong Lee
  • Patent number: 10692996
    Abstract: Systems, methods and apparatus incorporating Gallium Nitride heterostructure (Alx,Iny)Ga1-x-y N-materials in flexible, strainable and wearable radio frequency devices. These devices include (Alx,Iny)Ga1-x-y N-based high-electron mobility transistors (HEMTs), which enable amplification of microwave radio frequencies from approximately 300 MHz to approximately 300 GHz for flexible and conformal wireless transmission.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 23, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Nicholas R. Glavin, Kelson D. Chabak, Michael R. Snure
  • Patent number: 10693105
    Abstract: An OLED packaging method is provided, in which a first outer bound confinement layer is first formed and then, a first organic layer is formed on the first inorganic layer in an area enclosed by the first outer bound confinement layer so that facilities for forming the first organic layer can be diversified and an organic material used to form the first organic layer is not subjected to constraint in respect of viscosity thereof, whereby using an organic material with a reduced viscosity allows for better homogeneity of the first organic layer, the thickness reduced, and thus helping reduce a curving radius of the OLED package structure to realize rollable displaying with a reduced curving radius. Further, the first outer bound confinement layer helps block external moisture and oxygen from corroding the first organic layer in a sideway direction.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 23, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiangjiang Jin, Hsianglun Hsu
  • Patent number: 10685866
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert Robison, Veeraraghavan S. Basker, Reinaldo Vega