Abstract: A edge detection circuit has a D-type Flip Flop (D-FF) 11 having a reset node and an input node connected to an input terminal, a D-FF 12 connected to the D-FF 11, D-FF 13 having a set node and connected to the D-FF 12, D-FF 14 having set node and connected to the D-FF 13, a detection circuit 21, 22 for detecting an edge change of a control signal and output a detection signal when the control signal changes an inactive level (Hi level) to an active level (Lo level), and a control circuit 31, 51 for generating a set signal for set the D-FFs 13 and 14 when the control circuit receives the detection signal and the input signal IN indicates Hi level.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Abstract: An address generator circuit (21A) includes a shift register (28) for storing therein address data (AD) to be outputted. A plurality of memory circuits which are equal in one of the numbers of bits of X and Y addresses for specifying rows or columns of memory cell arrays and different in the other number, apply data to scan paths so that less significant bits of the addresses having the same number of bits are stored in a position closer to an input terminal. An XOR gate (27A) in the address generator circuit (21A) generates write data (DI) for writing RAMs (31, 32) from data (X0, Y0) stored in predetermined registers of the shift register (28).

Abstract: In a distributed computing system consisting of a plurality of computers each holding the computer reliability of its own, one of the computers includes a reliability management program, This reliability management program manages the program reliability required for each of a plurality of programs to be executed in the system. The reliability management program includes the steps of inquiring the computer reliability of each of the other computers to receive the computer reliability held in each of the other computers thereby preparing a computer information table, searching the table to find the values of the computer reliability of the computers corresponding to those of the program reliability of the individual programs, and allocating, on the basis of the result of the search, the individual programs to the individual computers.

Abstract: A method and apparatus for reducing the amount of corrupted data in a system for transmitting encoded data across a network, which system requires sychronization between encoding and decoding nodes, the method and apparatus involving (a) providing an indication of the reliability of the channel between the encoding and decoding nodes; (b) performing automatic resets at the nodes at intervals I; and (c) utilizing the indication of channel reliability to control the interval I. The interval I may be determined, for example, by the error rate on the channel for one or more preceding time interval S, and may be determined at either the encoding or decoding node.

Abstract: A signal selection and fault detection system receives multiple redundant sensor input signals that are processed through an equalizing and selecting network which outputs the midvalue signal. The system provides a variable fault monitoring threshold that provides the ability to detect for oscillatory faults among input signals that are less than 10% of static tracking tolerances for the inputs, while also assuring that nuisance fault detections are very improbable. The system provides a variable equalization rate that assures satisfactory blocking of oscillatory faults under dynamic conditions when signal disagreements are increased by gain tolerances between the input signals, and maintains high signal resolution of the output under such dynamic conditions. The system also provides cross-channel equalization of the selected midvalue signal in all operating channels to assure that all channels provide the same steady state output for only two input operation, while also maximizing fault blocking capability.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Abstract: A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.

Abstract: An error counting circuit is adapted to count a number of code errors of a main signal in an external apparatus which is coupled to an optical transmission path. The error counting circuit includes an error counter which counts error pulses received from the external apparatus and indicative of the number of code errors of the main signal in response to clock pulses having a predetermined period and outputting a counted value for each the predetermined period, and a mechanism for stopping a counting operation of the error counter when a power failure of the external apparatus occurs, so that an erroneous counting operation of the error counter is prevented.

Abstract: An Internet checksum for use by TCP/IP is generated in a single macro-instruction called a Block Add Octets instruction. Extraneous overhead of macro-instruction looping and bit masking is eliminated by combining checksum operations into a single macro-instruction using a block add approach. The programmer specifies the address in memory and the number of double-words of message data to be added together within a single instance of the Block Add Octets instruction so that looping and jump/branch instructions are not needed. The Block Add Octets instruction fetches all octets (8-bit data segments) contained in full double words from memory and adds them into the checksum. The method handles partial double words of data, full double words, and odd numbers of double words, whereby a double word consists of four octets. The checksum is calculated using one's complement arithmetic rather than two's complement, thereby increasing the speed of checksum calculation because the "end around carry" is eliminated.

Abstract: A method for detecting fault conditions on a multiplexed network having first and second busses. The method includes sensing a start of frame delimiter (SOF) for the first bus, and determining the state of the second bus when the SOF is sensed. If the state of the second bus has been passive over a first selected time period, the state of a differential between the first and second busses is determined. If the state of the differential between the first and second busses is not indicative of a pre-qualified start of frame delimiter, then a passive fault is indicated. Additionally, the method includes sensing an end of frame delimiter (EOF) for the first bus, and determining the state of the second bus when the EOF is sensed. If the state of the second bus has been active over a selected time period, then an active fault for the second bus is indicated. A system for performing the method is also disclosed.

Abstract: A data transmission method in a real-time data processing system, comprising a control unit and at least one function unit linked to this control unit through a data line, is described that permits noise-free and noise-insensitive transmission of data. In accordance with the invention, the data is stored in a buffer memory made up of a shift register and an intermediate storage, before being loaded into a main memory of the function unit. Transfer to the intermediate storage takes place only if certain conditions are satisfied that identify transmission faults. Before the data is stored in the main memory, the data is read-back into the control unit memory for the purposes of checking and there it is compared with the original data. If there is no correspondence, data transmission is performed again.

Abstract: In intermediate network nodes of high speed packet switching networks, when a message is modified, the invention proposes a method and an apparatus for calculating a modified FCS error code. Using the properties of calculations in the Galois Field, the implementation of the invention, specially in the intermediate Frame Relay network nodes, is reduced to a plurality of simple well known operators (90, 100, 120, 30); the implementation of the invention allows the usage of a plurality of small lookup tables (60, 70, 80, 110) as desired and thus avoiding large amounts of storage resources.

Abstract: A protect circuit that may be interconnected to two different data transmission lines and that provides enhanced error correction. The circuit includes first and second line build-out circuits and fixed delay buffers interconnected to the two transmission lines, as well as a controller and switch. The build-out circuits allow the data bits received from the two data transmission lines to be correlated. Each of the fixed delay buffers has a predetermined length and holds a sequence from one of the two transmission lines. The controller tests the correlated data bits from the build-out circuits to determine whether any coding rule violation has occurred. If a coding error, such as, for example, a hi-polar violation, is detected, the contents of the fixed delay buffer that includes the bit that does follow the predetermined coding rule is transmitted to the receiving station. Thus, both of the transmission lines are utilized in order to enhance the accuracy of the data transmitted to the receiving station.

Abstract: A semiconductor test system is to realize a pattern generation that makes possible to test memory devices having arbitrary cycle latency operations when using multiple pattern generators. A cycle shift circuit that outputs a delayed expected value signal by shifting the expected value by one cycle with the operating period of the pattern generator is arranged. A N to 1 selector that selects an arbitrary signal from the expected value signal output by the multiple pattern generators including itself and the delayed expected value signal output by the multiple pattern generators excluding itself is arranged. A cycle shift section is arranged for the output selected by the selector. An arbitrary cycle shift can be generated by the expected value pattern using the above multiple pattern generators.

Abstract: A diagnostic device for a port interface equipment (32) of a communications switching system (12), and at least one digital console (34) having a device (10) for selectively monitoring the communications data passing to either the port interface equipment (32) or the digital console (34) without affecting the communications data passing therebetween, and a device (42) for selectively and removably connecting the monitoring device between the port interface equipment (32) and a selected digital console (34) in order to monitor the communications data passing therebetween.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A distributed processor system includes a plurality of processors connected via a transmission medium. A control method for a distributed processor system includes the steps of judging, in each processor, its own receiving capability and performing abnormality processing on the basis of the result of the judgment.

Abstract: A memory controller parity system that detects both even and odd bit errors in memory addresses and global errors in memory data. The parity system detects errors in any memory system employing an address bus or data allocation map. It is effective for applications requiring random memory accesses as well as in blocked-data accesses such as in controller buffer memories for servicing disk file systems and tape storage systems. The controller stores data in memory together with a single appended global parity bit representing (n-1) bits from an n-bit address, thereby detecting both even and odd fixed errors over time. A p-bit identification register can be added to the controller to facilitate detection over time of global data errors arising from data allocation map errors during the data storage period. The single-bit parity scheme is compatible with existing single-bit parity memory systems.

Abstract: An apparatus and method for detecting and locating up to two symbols in error or erasures in an n.times.m A(n,m,t) parity coded bit array previously recorded on a multi-track storage device where n is a prime number, m.ltoreq.n, wherein at least one non-zero syndrome of m rotated and column summed syndromes is derived. The method includes an iterative process using an incremented tracking variable and testing of the cyclic equivalence of three derived vectors to isolate the number and location of the array column or columns containing the error or errors. Each derived vector is the modulo 2 sum of a selected syndrome and a selected rotated vector. Cyclic equivalence of between a derived vector and a selected rotated one of the other derived vectors for any given iteration establishes the error or errors and their column location or locations. An extension is shown for detecting and locating up to three errors or erasures.