Patents Examined by Phung M. Chung
  • Patent number: 11128315
    Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Myung Jin Jo, Dae Sung Kim, Wan Je Sung
  • Patent number: 11128318
    Abstract: The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11126500
    Abstract: Systems and methods for error detection and correction with integrity checking are provided. A method includes first processing both data vector bit values and integrity vector bit values using a single error correction and double error detection (SECDED) code to generate check bit values, where the SECDED code is configured to allow both: (1) a detection and correction of a single error in the data vector values, or (2) an indication of an uncorrectable error, where the uncorrectable error corresponds to more than a single error in the data vector bit values or a single error or a multi-bit error in the integrity vector bit values. The method further includes second processing the check bit values and indicating an uncorrectable error for more than a single error in the data vector bit values or for a single error or a multi-bit error in the integrity vector bit values.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 21, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jay S. Fuller
  • Patent number: 11115157
    Abstract: The disclosure provides a method for scheduling an uplink control channel (PUCCH) in a next generation/5G wireless access network. The method of a terminal for scheduling a PUCCH may include: receiving, from a base station, timing relationship setting information between a downlink data channel (PDSCH) and a PUCCH; and scheduling the PUCCH on the basis of the timing relationship setting information.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 7, 2021
    Assignee: KT CORPORATION
    Inventors: Kyujin Park, Woo-jin Choi
  • Patent number: 11099749
    Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 24, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
  • Patent number: 11101925
    Abstract: Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Peng Li, Masashi Shimanouchi
  • Patent number: 11095315
    Abstract: Dynamically adjusting an error correction effort level of a storage device, including: receiving, from a storage array controller, an error correction effort level to perform when attempting to read data from the storage device; identifying that an attempt to read the data resulted in an error; and determining whether an amount of error correction effort level required to attempt to correct the error exceeds the error correction effort level to perform when attempting to read data from the storage device.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 17, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ethan Miller
  • Patent number: 11093390
    Abstract: A memory system includes a memory device; a short super block detecting unit suitable for forming, when one or more initial bad blocks remain in an original super block after a re-mapping operation is performed and a number of the initial bad blocks is equal to or less than a predetermined threshold value within the original super block, a short super block with memory blocks included in the original super block; a bitmap generating unit suitable for generating a bitmap representing whether each of the memory blocks included in the short super block is a normal block or an initial bad block; and a processor suitable for controlling the memory device to simultaneously perform a normal operation on normal blocks among the memory blocks included in the short super block based on the bitmap.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Lee
  • Patent number: 11082063
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11073553
    Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wilson Pradeep, Prakash Narayanan
  • Patent number: 11068343
    Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Patent number: 11070235
    Abstract: The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 20, 2021
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11063609
    Abstract: One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 11050438
    Abstract: A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Kim
  • Patent number: 11048582
    Abstract: A method for programming a non-volatile memory in a programming operation is provided. The non-volatile memory has a number of cells and each of part of the cells store data having at least 2 bits at least corresponding to a first page and a second page. The method includes the following steps. At least one programming pulse is provided. At least one first program-verify pulse is provided. A program-fail-reference signal is enabled. At least one second program-verify pulse is provided after enabling the program-fail-reference signal.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Chang Huang, Kun-Tse Lee
  • Patent number: 11048573
    Abstract: A data processing system includes a plurality of memory boards including a plurality of memory devices, and an error management controller that generates second error information based on plural pieces of first error information respectively received from each of the memory devices, and a memory error analysis device that analyzes the second error information received from the memory boards.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Eung-Bo Shim
  • Patent number: 11047910
    Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Wilson Pradeep, Prakash Narayanan
  • Patent number: 11044070
    Abstract: Methods, systems, and apparatus for EM communications. One of the methods includes determining, at a first device, that a second device is present; initiating a half duplex communication with the second device; configuring communication with the second device including determining whether full duplex communication is available; in response to a determination that full duplex communication is not available, communicating with the second device in half duplex mode; and in response to a determination that full duplex communication is available, communication with the second device in full duplex mode.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 22, 2021
    Assignee: Keyssa Systems, Inc.
    Inventors: Edward T. Pak, Roger D. Isaac
  • Patent number: 11038533
    Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p. The method includes each column in the p×(k+r) array has an even parity and symbol i in column r+j, for 0?i?p?1 and 0?j?r?1, is the XOR of symbols in a line of slope j taken with a toroidal topology modulo p in the k columns starting in symbol i of column 0.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven R. Hetzler
  • Patent number: 11018694
    Abstract: Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 25, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Mark Allen Gravel