Patents Examined by Phung M. Chung
  • Patent number: 11463109
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 4, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 11456756
    Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 5/16, 6/16, or 7/16. The parity check matrix includes an A matrix of M1 rows and K columns expressed by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of M1 rows and M1 columns having a step structure, a Z matrix being a zero matrix of M1 rows and N?K?M1 columns, a C matrix of N?K?M1 rows and K+M1 columns, and a D matrix being an identity matrix of N?K?M1 rows and N?K?M1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 27, 2022
    Assignee: SONY CORPORATION
    Inventors: Makiko Yamamoto, Yuji Shinohara
  • Patent number: 11442811
    Abstract: Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Bi Woong Chung, Jung Hwan Lee, Se Yeong Huh, In Jae Koo
  • Patent number: 11442810
    Abstract: A memory includes: a memory core including sequentially disposed N data cell regions and an ECC cell region respectively suitable for storing N data pieces of K bits and a corresponding ECC of M bits; and an error correction circuitry suitable for generating the ECC based on the data pieces and error-correcting the data pieces based on the ECC, through a check matrix configured by a message part of a [M×(K*N)] bit-dimension and an ECC part of a [M×M] bit-dimension, wherein the message part includes N characteristic indicator groups of a [M/2×K] bit-dimension, respectively corresponding to the data pieces, and each including K indicators of a [M/2×1] bit-dimension and having the same value, and wherein a hamming distance between the indicators respectively corresponding to the data pieces stored in neighboring ones among the data cell regions is 1 or M/2.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoiju Chung, Jang Ryul Kim
  • Patent number: 11435940
    Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 6, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Mohamed Azimane
  • Patent number: 11430525
    Abstract: According to one embodiment, a memory device, includes a first memory cell, and a second memory cell adjacent to the first memory cell; and a sequencer configured to, when data is read from the first memory cell: perform a first read operation on the second memory cell; perform a second read operation on the first memory cell; perform a third read operation on the first memory cell by applying a voltage different from that applied in the second read operation to a gate of the second memory cell; and generate first data stored in the first memory cell and second data for correcting the first data, based on results of the first to third read operations.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoko Araya, Mitsuaki Honma
  • Patent number: 11416352
    Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 16, 2022
    Assignee: ARTERIS, INC.
    Inventors: Jean Philippe Loison, Benoit de Lescure, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad, Mohammed Khaleeluddin
  • Patent number: 11398837
    Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for rate-matching a stream of bits encoded using polar codes. An exemplary method generally includes encoding K information bits using a polar code with a mother code length, N, to generate a stream of encoded bits storing a portion of the encoded bits in a circular buffer of size N reordering P blocks of the circular buffer according to row weights of a Hadamard matrix J interlacing the encoded bits of the blocks having a same row weight selecting, based on the row weights, a subset of the encoded bits in the blocks to modify modifying the selected subset of the encoded bits and transmitting the encoded bits in the P blocks, subsequent to modifying the selected subset of the encoded bits, via transmission resources.
    Type: Grant
    Filed: August 12, 2017
    Date of Patent: July 26, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Liangming Wu, Hao Xu
  • Patent number: 11394403
    Abstract: Methods and system for error correction based on rate adaptive LDPC codes with flexible column weights in the parity check matrices are described. Data is encoded according to a first encoding parity check matrix of a first Low Density Parity Check (LDPC) code to obtain a first codeword with first parities. The first codeword is encoded according to a second encoding parity check matrix of a second LDPC code to obtain second parities. The first codeword is received. Responsive to failure of error correction of the first codeword based on the first parities, the second parities are received. The first codeword is corrected based on the second parities and a decoding parity check matrix of a rate adaptive LDPC code that is constructed by vertically concatenating the second encoding parity check matrix and the first encoding parity check matrix and adding an all-zero sub-matrix to complete its dimensions.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: July 19, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Eyal En Gad, Sivagnanam Parthasarathy, Zhengang Chen, Mustafa N. Kaynak, Yoav Weinberg
  • Patent number: 11392454
    Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoyoun Kim, Kijun Lee, Chanki Kim, Myungkyu Lee
  • Patent number: 11379289
    Abstract: Detecting data corruption in a storage system includes examining portions of the data for encryption anomalies and providing an indication in response to detecting an encryption anomaly. The encryption anomalies may be based on entropy of the data. The entropy of the data may vary based on an inherent nature of the data. One of the portions of data may be deemed to be encrypted in response to an entropy value exceeding a predetermined threshold. The predetermined threshold may be based on prior data accesses. The predetermined threshold may be determined using machine learning. Portions of the data may be examined for encryption anomalies during data accesses. Data accesses may be suspended in response to detecting an encryption anomaly. Encryption anomalies may include data that is flagged to be encrypted not being detected as being encrypted and/or data that is flagged to not be encrypted being detected as being encrypted.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 5, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Brett A. Quinn
  • Patent number: 11342944
    Abstract: A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 24, 2022
    Assignee: UNTETHER AI CORPORATION
    Inventor: William Martin Snelgrove
  • Patent number: 11328777
    Abstract: Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Theodore T. Pekny
  • Patent number: 11317434
    Abstract: A determination is made whether each predetermined bit of a plurality of predetermined bits of a Semi-Persistent Scheduling (SPS) scheduling assignment for a user equipment (UE) has a respective predetermined value required to validate the SPS scheduling assignment. In circumstances where each predetermined bit of the plurality of predetermined bits of a Semi-Persistent Scheduling (SPS) scheduling assignment is determined to have a respective predetermined value required to validate the SPS scheduling assignment, an action corresponding to SPS is performed. In circumstances where at least one predetermined bit of the plurality of predetermined bits of an SPS scheduling assignment is determined to fail to have a respective predetermined value required to validate the SPS scheduling assignment, the SPS scheduling assignment is discarded and the action is not performed.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 26, 2022
    Assignee: Unwired Planet International Limited
    Inventors: Aris Papasakellariou, Soeng Hun Kim, Gert-Jan Van Lieshout
  • Patent number: 11315653
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and method for controlling the DRAM. The DRAM has a first operation mode and a second operation mode. The DRAM includes a control module and a connecting module. The connecting module includes an input/output (I/O) pad and a determining circuit. The I/O pad is configured to receive a first input signal. The determining circuit includes a detector and a first determining unit. The detector is configured to compare the first input signal to a reference signal so as to generate a first signal. The first determining unit is configured to receive the first signal and generate a first output signal according to the first signal. The control module is configured to control the DRAM being operated under the first operation mode or the second operation mode according to the first output signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 11283469
    Abstract: An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 22, 2022
    Assignee: Infineon Technologies AG
    Inventors: Wieland Fischer, Bernd Meyer
  • Patent number: 11283542
    Abstract: An encoding circuit includes an allocator to allocate a symbol to bit-strings within a first frame, a converter to convert values of target-bit-strings that exclude a predetermined-bit-string so that, as a region within the constellation is closer to a center of the constellation, a number of symbols allocated in the region is larger, a generator to generate an error-correction-code of the bit-strings, and an insertion circuit to delay the error-correction-code and insert the error-correction-code in the predetermined-bit-string within a second frame that succeeds the first frame, wherein the allocator allocates, to the bit-strings, one symbol that corresponds to the values of the target-bit-strings, the one symbol being within a quadrant that corresponds to a value of the predetermined bit-string, and wherein the converter switches, based on the value of the predetermined-bit-string, association relationships between the values of the target-bit-strings before and after the conversion.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: March 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yohei Koganei, Kiichi Sugitani
  • Patent number: 11272402
    Abstract: A resource upgrade predictor can be operable to receive, from a first network node device, traffic information. Based on the traffic information, the resource upgrade predictor can obtain network utilization data related to other network node devices having a similar interference characteristic (e.g., signal-to-noise ratio) to the first network node device. The resource upgrade predictor can use this network utilization data to determine a demand (e.g., demand level, demand point) at which at least a defined value related to a transmission link capacity associated with transmissions between the first network node device and the user equipment, is attained (e.g., a percentage of physical resource block loading).
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 8, 2022
    Assignees: AT&T INIELLECTUAL PROPERTY I, L.P., AT&T MOBILITY II LLC
    Inventors: Sheldon Meredith, Zachary Meredith, Thomas Kiernan
  • Patent number: 11271593
    Abstract: A systematic encoder reliably transferring a source data block (SDB) is configured for an outer transform matrix and an inner transform matrix. An inner encoder receives the SDB and generates an output constraint block (OCB) as an SDB image under an inverse of a submatrix of the inner transform matrix. An outer encoder receives a fixed data block (FDB) and the OCB and generates a transform output block (TOB) as a transform input block (TIB) image under the outer transform matrix. The TIB contains the FDB transparently in a sub-block of the TIB, and the TOB contains the OCB transparently in a sub-block of the TOB. The inner encoder receives the TOB and generates a transmitted code block (TCB), transparently containing the SDB in a sub-block therein.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: March 8, 2022
    Assignee: POLARAN YAZILIM BILISIM DANISMANLIK ITHALATIHRACAT SANAYI TICARET LIMITED SIRKETI
    Inventor: Erdal Arikan
  • Patent number: 11265024
    Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data structures, groups or streams.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 1, 2022
    Assignee: Primos Storage Technology, LLC
    Inventor: Robert E. Cousins