Patents Examined by Phung My Chung
  • Patent number: 7237158
    Abstract: The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures are determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Brett M. Debenham
  • Patent number: 7234087
    Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 19, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito
  • Patent number: 7231574
    Abstract: A method and system for extensions to earlier patents dealing with the implementation of the InterSystem Channel (ISC) link architecture. First, it describes hardware state machines that handle all valid link messaging sequences without any processor involvement. These state machines also process larger commands and responses that may be divided into multiple frame segments. Finally, the missing frame detection is expanded for the multi frame segment commands and responses.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 7228480
    Abstract: A method for encoding a bit stream to meet a minimum bit transition requirement includes providing uncoded bits, determining whether the uncoded bits meet the minimum bit transition requirement, and replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: June 5, 2007
    Assignee: Maxtor Corporation
    Inventors: John McEwen, legal representative, Ara Patapoutian, Bernie Rub, Peter McEwen, deceased
  • Patent number: 7225391
    Abstract: A method for generating a linear block code is disclosed. A message is broken up into a plurality of sets of bits. A first group of sets is processed to determine a first partial linear block code. An adjusted partial linear block code is generated from the partial linear block code. A second group of sets is processed to determine a second partial linear block code. The adjusted partial linear block code and the second partial linear block code are combined into a single value.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 29, 2007
    Assignee: Altera Corporation
    Inventor: Peter D. Bain
  • Patent number: 7225376
    Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: Joerg Georg Appinger, Michael Juergen Kessler, Manfred Schmidt
  • Patent number: 7222278
    Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 22, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Charles E. Moore, Xiaoyang Zhang, Jeffrey R. Rearick
  • Patent number: 7219283
    Abstract: Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an output connected to a serial data output lead. A first gate has an output connected to the control input of the first buffer, a scan output enable input connected to a scan circuitry control output lead, and a lock out signal input. A second buffer has an input connected to a test data output lead, an input connected to a buffer enable output lead, and an output connected to a serial data output lead. This structure provides for selecting data outputs between the TAP and internal scan test ports.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: May 15, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7219272
    Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: May 15, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co. Ltd.
    Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
  • Patent number: 7219287
    Abstract: A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 15, 2007
    Assignee: Xilinx, Inc.
    Inventors: Shahin Toutounchi, Andrew M. Taylor
  • Patent number: 7219275
    Abstract: A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 15, 2007
    Assignee: International Business Machines Corporation
    Inventors: Tom Y. Chang, William V. Huott, Thomas J. Knips, Donald W. Plass
  • Patent number: 7219285
    Abstract: A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: May 15, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoharu Tanaka, Noboru Shibata, Toru Tanzawa
  • Patent number: 7216279
    Abstract: An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: May 8, 2007
    Assignee: LSI Logic Corporation
    Inventors: Kevin J. Gearhardt, Anita M. Ekren
  • Patent number: 7216268
    Abstract: A channel characteristic of a transmission channel between a remote terminal and a central office is estimated by collecting information in the remote terminal, transferring this information from the remote terminal to the central office and matching the received information at the central office with a channel and remote terminal simulation model. The values of parameters of the latter simulation model, which define the channel characteristic to be estimated, are determined as a result of the matching process. The information collected by the remote terminal typically is information that is automatically collected by the remote terminal for operational purposes. such as equalizer setting and, bit allocation.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: May 8, 2007
    Assignee: Alcatel
    Inventors: Frank Ryckebusch, Stan Claes
  • Patent number: 7213186
    Abstract: A new built-in self-test circuit device for testing an embedded memory array is achieved. The device comprises a pattern generator unit that executes a testing sequence to automatically write and read locations in an embedded memory. A comparison unit compares data read from the embedded memory and expected data provided by the pattern generator. An error signal is turned ON by the comparison unit when the data read does not match the data provided. An error release unit generates an error stop signal. The error stop signal is turned ON when the error signal is turned ON. The pattern generator unit testing sequence is stopped when the error stop signal is turned ON and is re-started when the error stop signal is turned OFF. The error stop signal is turned OFF when an external device asserts an error release signal.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: May 1, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jinn-Yeh Chien
  • Patent number: 7210088
    Abstract: A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: April 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Paul W. Coteus, Alan G. Gara
  • Patent number: 7210078
    Abstract: A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output pulses 4 toggled as desired. Also a circuit 1 for evaluating an output 4 of a sequential circuit 2 that determines if the output pulses 4 toggled as desired.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Brian D. Borchers, Stephen W. Spriggs
  • Patent number: 7210086
    Abstract: The invention relates to a design analysis technique for a test pattern analysis of chips via automatic test equipment (ATE) or a circuit simulation to detect potential design weakness or abnormal behavior in real customer application faults. Problems are solved by comprising a simulation procedure stored in an LRT database of automatic test equipment (ATE), defining test conditions and test patterns which execute and generate continuously for a time given by a user, applying the test stimuli and test conditions to a device under test (DUT) and starting the long running test (LRT), stopping the test automatically if any application faults occur and logging the failure time and timely test sequence and starting another test again until a given maximum number of tests are reached.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Infineon Technologies AG
    Inventor: Eric Liau Chee Hong
  • Patent number: 7203869
    Abstract: A method and apparatus for generating a test stream wherein tests of digital TV software at various levels and various digital broadcast standards can be supported. The apparatus includes a data generator module for generating test data by referring to a database based on demands of a user, a data writer module for fetching the test data generated by the data generator module and writing the fetched test data into a text or XML data, a data transformation module for transforming the written text or XML data into a transport stream, and a database in which information needed for the modules to perform their own functions is stored and from which the stored information is fetched. The method of invention may similarly follow the functions of the apparatus.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-hee Gwak
  • Patent number: 7200792
    Abstract: In an apparatus for data transmission in a communication system, a turbo encoder encodes data bits to generate systematic bits and parity bits, and a rate matcher matches the systematic bits and parity bits. A first interleaver writes the rate-matched systematic bits on a row by row basis, and performs inter-column permutation. A second interleaver writes the rate-matched parity bits on a row-by-row basis, and performs inter-column permutation. A modulator alternatively collects the permutated bits on a column by column basis from the first and second interleavers, and maps collected bits from the first and second interleavers onto one modulation symbol, wherein a size of the first interleaver is equal to a size of the second interleaver.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 3, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hun-Kee Kim, Gin-Kyu Choi, Jae-Seung Yoon, Noh-Sun Kim, Jun-Sung Lee, Yong-Suk Moon