Abstract: In an apparatus for data transmission in a communication system, a turbo encoder encodes data bits to generate systematic bits and parity bits, and a rate matcher matches the systematic bits and parity bits. A first interleaver writes the rate-matched systematic bits on a row by row basis, and performs inter-column permutation. A second interleaver writes the rate-matched parity bits on a row-by-row basis, and performs inter-column permutation. A modulator alternatively collects the permutated bits on a column by column basis from the first and second interleavers, and maps collected bits from the first and second interleavers onto one modulation symbol, wherein a size of the first interleaver is equal to a size of the second interleaver.

Abstract: Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.

Abstract: An error correction coding apparatus includes a parity check matrix generation unit which generates a parity check matrix having a number of elements having a value of 1 in each row thereof, having a predetermined number of elements having a value of 1 in each column thereof, and having the other elements having a value of 0; a parity check matrix adjustment unit which receives the parity check matrix from the parity check matrix generation unit, searches the parity check matrix for a cycle forming group of four elements positioned at respective vertexes of a rectangle and having a value of 1, and when there is at least one cycle forming group, replaces the value of 1 of at least one element of the cycle forming group with the value 0 of another element, to output a adjusted parity check matrix without a cycle forming group therein; and an LDPC coding unit which receives the adjusted parity check matrix from the parity check matrix adjustment unit and receives an m-bit message word to perform LDPC coding.

Abstract: A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix includes at least two consecutive complementary columns. The present invention also relates to a method for determining a syndrome, as well as a coding and decoding circuit.

Abstract: A semiconductor apparatus comprises a processor having an instruction register inside thereof, a pseudorandom number generating device activated in response to a test operation and generating pseudorandom numbers, an input switchover device for switching over between data input in normal operation and input of the pseudorandom numbers from the pseudorandom number generating device in the test operation to thereby output the data or pseudorandom numbers to the instruction register. The pseudorandom numbers generated in the pseudorandom number generating device are inputted to the instruction register via the input switchover device so that the random instructions are implemented and a random test is implemented with an activation rate equivalent to the same in the normal operation.

Abstract: In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.

Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Abstract: A failure analysis system of a logic LSI incorporates software therein. The analysis system includes a function to record the terminal signal information of said logic LSI in synchronization with a clock and a function to reproduce said recorded terminal signal information in synchronization with the clock. The analysis system further includes a function to compare said reproduced terminal signal information with the terminal signal information of a normal logic LSI.

Abstract: A test apparatus for testing an electronic device, includes a test module for sending and/or receiving a test signal to and/or from the electronic device, a test head including a plurality of Test Head (TH) slots for detachably holding the test module, a diagnosis module for performing diagnosis of the test module, and a coupling device including a plurality of Performance Board (PB) slots being electrically coupled to the TH slots respectively for detachably holding the diagnosis module. The diagnosis module held in one of the PB slots diagnoses the test module held in one of the TH slots being electrically coupled to one of the PB slots.

Abstract: In a disk array system of RAID (level 5) improving the system performance by distributing data, duplicated fields are allocated in a parity group in order to reduce an overhead of data write. In the data write process, write data is tentatively and duplicately written in the duplicate fields. At this time, a write completion is reported to CPU. The parity is generated later at a proper timing and written in a SCSI drive. Generating a parity and writing data can be efficiently scheduled.

Abstract: A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the plurality of cores. The master controller is coupled with the plurality of slave controllers in a star configuration. The master controller is configured to allow test data to be input directly to a portion of the plurality of slave controllers in parallel. The portion of the plurality of slave controllers can include more than one slave controller.

Abstract: A method for testing an electronic module having a memory cell device includes writing an information item to the memory cell device at a first clock frequency and then reading-out the information item from the memory cell device at a second clock frequency. The read out information item is reflected at a reflection point and is written back to the memory cell device at the second clock frequency. The reflected information unit is then read-out from the memory cell device with the first clock frequency.

Abstract: A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied digital input signal. The digital input signal is then varied and another figure of merit is calculated for the fault free and the known faulty circuit for the new input signal. This is repeated a number of times, the digital input signal being varied each time. An optimum test signal is selected based on the determined figures of merit.

Abstract: A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

Abstract: Propagating an error through a network includes receiving a network having propagation paths and nodes, where a propagation path has one or more nodes and a node is associated with a variable operable to have a value during simulation. A tag of a tag set is assigned to the value. The tag set includes at least two signed tags, positive tag representing a positive error and a negative tag representing a negative error, and an unsigned tag representing an error having an unknown sign. The tag is propagated along the propagation path to yield intermediate tags, where at least one intermediate tag is an unsigned tag formed from at least two signed tags. A final tag is determined in accordance with the intermediate tags in order to propagate an error through the network.

Abstract: The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a parallel port) for testing the open or short conditions of the ports through walk 1? and a walk 0? logic tests. The testing module not only can check the open condition of a parallel port, but also can check the open and short conditions of a parallel port and a serial port.

Abstract: A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency. The system further includes a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal. A sub-chip sampler is configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency of the system clock signal.

Abstract: A method and device for handling received data units at the receiving peer of a predetermined data unit exchange protocol at a given layer is described, where said method and device carry out a limited ARQ mechanism for received data units, and are characterised by providing the possibility of storing corrupted copies of received data units, and providing a data unit to an upward release handler on the basis of one or more stored corrupted copies of a given data unit after a triggering event terminating the operation of the retransmission request procedure for the given data unit.

Abstract: An error rate of a TFCI of a transmission data format, and when an error rate of the TFCI becomes worse, a request to increase only the power of the TFCI is issued to the transmitter. The error rate of the TFCI is computed from the error detection result of a TrCH. Especially when the data length of the TrCH is relatively short, this method is not applied, but wasteful power consumption increases. When the data length of the TrCH is long, this method is applied to realize error rate control with the wasteful power consumption minimized.

Abstract: Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence.