Abstract: Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: A plurality of transmit antennas of a radio transmission device and a plurality of receive antennas of a radio reception device are located under the sea that is a line-of-sight environment, wherein the radio transmission device selects a frequency channel to be used based on an index value per frequency channel indicating orthogonality between the transmit and receive antennas defined based on a distance between the transmit and receive antennas and an angle indicating a direction of arrival of a radio signal, an interval between the plurality of transmit antennas, an interval between the plurality of receive antennas, and a modulation scheme, the distance between the transmit and receive antennas and the angle indicating the direction of arrival of the radio signal estimated by the radio reception device, and a desired bit error rate to be predetermined, selects the modulation scheme for providing a maximum transmission capacity per the selected frequency channel, separates transmission data into a pluralit

Abstract: A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the thi

Abstract: Various embodiments of the present disclosure provide a method for information sharing. The method which may be performed by a first network node comprises receiving a first measurement report from a terminal device. The terminal device may be capable of communicating with the first network node over a first connection. The method further comprises transmitting first measurement information based at least in part on the first measurement report to a second network node. The terminal device may be capable of communicating with the second network node over a second connection.

Abstract: A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.

Abstract: A system and method compensate for latency, where the system includes a transmit module and a receive module that implements a DLL in a pseudo synchronous communications link. The method includes determining maximum data latency based on synchronous latencies and analog delays; measuring an actual data path latency by determining a delay in receiving a test pattern transmitted from the transmit module at the receive module using a common synchronization pulse provided the transmit and receive modules simultaneously or with a known fixed latency separation during calibration; determining a latency difference between the determined maximum data latency and the measured data path latency; and compensating for the latency difference for a subsequent data signal transmitted from the transmit module in the pseudo synchronous communications link, such that a total latency of the system with regard to the subsequent data signal is equal to the maximum data latency for the system.

Abstract: A radio apparatus correlates signal data with stored synchronization data to determine correlation data. The signal data represents a received radio-frequency signal that encodes a data frame, which has a synchronization preamble with a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The radio apparatus identifies a set of peaks in the correlation data, and uses a timing criterion to identify a plurality of subsets of the set of peaks, such that time values of the peaks of each identified subset satisfy the timing criterion. The radio apparatus calculates a correlation score Cj for each of the identified subsets from correlation values of the subset's peaks, and uses the correlation scores Cj to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.

Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.

Abstract: A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.

Abstract: Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

Abstract: A front-end module of a wireless device can replace a passive duplexer with an active duplexer that uses metamaterial matching circuits. The active duplexer can be formed from a power amplifier circuit and a low noise amplifier circuit that each include a metamaterial matching circuit. The combination of a power amplifier circuit and a low noise amplifier circuit that each utilize metamaterials to form the associated matching circuit can provide the functionality of a duplexer without including the additional circuitry of a stand-alone or passive duplexer. Thus, in certain cases, the front-end module can provide duplexer functionality without including a separate duplexer. Advantageously, in certain cases, the size of the front-end module can be reduced by eliminating the passive duplexer. Further, the loss introduced into the signal path by the passive duplexer is eliminated improving the performance of the communication system that includes the active duplexer.

Abstract: The intelligent measurement and control communication network at least includes at least one management node and at least one common node. The whole intelligent measurement and control communication network is logically divided into a control plane and a service plane. The control plane selects a routing strategy with the shortest path to cause each management node on the control plane to communicate with all common nodes. The service plane is divided into multiple task subnets according to tasks performed by each node, and each task subnet may select different routing strategies according to task requirements of this task subnet. According to the application and scenario needs of the tasks, the control plane combines externally changed parameters and utilizes machine learning to generate a new mathematical model in real time and sends a new task instruction to the service plane.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a ?3-dB corner frequency of 40 MHz.

Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

Abstract: Methods, systems, and apparatus for monitoring and controlling electronic devices using wired and wireless protocols are disclosed. The systems and apparatus may monitor their environment for signals from electronic devices. The systems and apparatus may take and disambiguate the signals that are received from the devices in their environment to identify the devices and associate control signals with the devices. The systems and apparatus may use communication means to send control signals to the identified electronic devices. Multiple apparatuses or systems may be connected together into networks, including mesh networks, to make for a more robust architecture.

Abstract: A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.