Patents Examined by Pierre-Michel Bataille
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Patent number: 11720486Abstract: The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.Type: GrantFiled: August 11, 2020Date of Patent: August 8, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yen-Ju Lu, Chao-Wei Huang
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Patent number: 11709772Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.Type: GrantFiled: July 29, 2022Date of Patent: July 25, 2023Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, James G. Wayda
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Patent number: 11709619Abstract: A data processing method includes receiving a message related to performance of a storage device, the message including an indicator value regarding the performance in a first time period, and a timestamp associated with the first time period. A status record of the storage device, including the number of received indicator values in a second time period including the first time period, is determined based on the timestamp, wherein the number of the received indicator values is less than a threshold number and can be updated based on the indicator value. The performance in the second time period can be determined based on the indicator value and the received indicator values in response to determining that the updated number of the received indicator values reaches the threshold number. Thus, the performance of the storage device can be quickly and accurately determined, and the consumption of computing resources is reduced.Type: GrantFiled: December 15, 2021Date of Patent: July 25, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Shijie Zhao, Colin Yuanfei Cai, Qirong Wang, Bei Gao
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Patent number: 11704024Abstract: A memory sub-system performs a first media management operation among a plurality of individual data units of a memory device after a first interval, the first media management operation comprising a first algebraic mapping function, and performs a second media management operation among a first plurality of groups of data units of the memory device after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units, the second media management operation comprising a second algebraic mapping function.Type: GrantFiled: July 27, 2020Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Ying Yu Tai, Ning Chen, Jiangli Zhu
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Patent number: 11704031Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.Type: GrantFiled: January 22, 2021Date of Patent: July 18, 2023Inventor: Dongsik Cho
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Patent number: 11704237Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.Type: GrantFiled: January 7, 2022Date of Patent: July 18, 2023Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, James G. Wayda
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Patent number: 11705207Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.Type: GrantFiled: November 24, 2020Date of Patent: July 18, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
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Patent number: 11698759Abstract: A clustered storage system may include potentially many different nodes. A node may mount a virtual storage volume for the use of a container application at the node. The node may receive a request from a different node and respond by indicating whether the virtual storage volume is in active use. In this way, the clustered storage system may safely but forcibly unmount a virtual storage volume having a failed or hanging mount point so that the volume may be mounted on a different node.Type: GrantFiled: November 29, 2021Date of Patent: July 11, 2023Assignee: Pure Storage, Inc.Inventors: Dinesh Israni, Vinod Jayaraman, Goutham Rao
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Patent number: 11693770Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.Type: GrantFiled: September 1, 2021Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventors: Shinichi Kanno, Naoki Esaka
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Patent number: 11687459Abstract: Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.Type: GrantFiled: April 14, 2021Date of Patent: June 27, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Michael Malewicki, Thomas McGee, Michael S. Woodacre
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Patent number: 11687450Abstract: A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.Type: GrantFiled: October 1, 2020Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventors: Beom Ju Shin, Yun Jung Yeom
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Patent number: 11681449Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.Type: GrantFiled: August 3, 2020Date of Patent: June 20, 2023Inventor: Dongsik Cho
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Patent number: 11681632Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.Type: GrantFiled: October 6, 2020Date of Patent: June 20, 2023Assignee: Rambus Inc.Inventor: Frederick A. Ware
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Patent number: 11681614Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.Type: GrantFiled: September 12, 2022Date of Patent: June 20, 2023Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, James G. Wayda
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Patent number: 11675519Abstract: The embodiments set forth techniques for facilitating processing checkpoints between computing devices. A method can be performed by at least one first computing device configured to interface with a first server computing device cluster, and include (1) processing objects managed by the first server computing device cluster, where the objects are stored across at least two first partitions associated with the first server computing device cluster, (2) detecting a condition to facilitate a processing checkpoint with at least one second computing device configured to interface with a second server computing device cluster, where the objects are mirrored—but stored differently across at least two second partitions associated with the second server computing device cluster, (3) gathering, from each partition of the at least two first partitions, information associated with a particular number of last-processed objects, and (4) providing the information to the at least one second computing device.Type: GrantFiled: December 1, 2020Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Krishna G. Pai, Alexander D. Holmes, M. Mansur Ashraf, Alaukik Aggarwal
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Patent number: 11669453Abstract: This application discloses a data prefetching method, including: receiving, by a home node, a write request sent by a first cache node after the first cache node processes received data; performing, by the home node, an action of determining whether the second cache node needs to perform a data prefetching operation on the to-be-written data; and when determining that the second cache node needs to perform a data prefetching operation on the to-be-written data, sending, by the home node, the to-be-written data to the second cache node. Embodiments of this application help improve accuracy and certainty of a data prefetching time point, and reduce a data prefetching delay.Type: GrantFiled: February 23, 2021Date of Patent: June 6, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Tao Liu
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Patent number: 11663118Abstract: In some examples, a device includes a set of data storage elements, wherein each data storage element of the set of data storage elements is associated with a respective valid address vector, and wherein a bit flip in any bit of any of the valid address vectors leads to one of a set of invalid address vectors not associated with any of the set of data storage elements. The device also includes a decoder configured to receive a first address vector as part of a request and to check whether the first address vector corresponds to one of the valid address vectors or to one of the invalid address vectors. The decoder is also configured to select an associated data storage element in response to receiving the request and in response to determining that the first address vector corresponds to one of the valid address vectors.Type: GrantFiled: March 10, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies AGInventor: Jens Barrenscheen
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Patent number: 11657877Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: GrantFiled: July 2, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Patent number: 11650755Abstract: A memory system having memory components and a processing device to receive, from a host system, write commands to store data in the memory components, store the write commands in a buffer, and execute at least a portion of the write commands. For example, this write buffer capacity can be represented by write credit values on the host and the subsystem. The processing device determines an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands, and signals the host system to receive information identifying the amount of available capacity, without a pending information request received from the host system.Type: GrantFiled: September 11, 2020Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Trevor Conrad Meyerowitz, Dhawal Bavishi
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Intelligent write-amplification reduction for data storage devices configured on autonomous vehicles
Patent number: 11650746Abstract: Systems, methods and apparatus of intelligent write-amplification reduction for data storage devices configured on autonomous vehicles. For example, a data storage device of a vehicle includes: one or more storage media components; a controller configured to store data into and retrieve data from the one or more storage media components according to commands received in the data storage device; an address map configured to map between: logical addresses specified in the commands received in the data storage device, and physical addresses of memory cells in the one or more storage media components; and an artificial neural network configured to receive, as input and as a function of time, operating parameters indicative a data access pattern, and generate, based on the input, a prediction to determine an optimized data placement scheme. The controller is configured to adjust the address map according to the optimized data placement scheme.Type: GrantFiled: September 5, 2019Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Poorna Kale, Robert Richard Noel Bielby