Abstract: A serial data receiving device comprises a first memory means for storing serial data while shifting the data bit by bit whenever receiving each one bit of the data and converting the serial data into parallel data when all the bits constituting the serial data are stored; a first detecting means for detecting the storage of all the bits constituting the serial data in the first memory means, a second memory means for storing a signal allowing the serial data to be received in accordance with the detection result by the first detecting means, and a first control means for controlling the reception of the serial data (outputting a hand-shake signal or transfer clock, for example) in accordance with the stored contents in the second memory means. A serial data transfer apparatus is equipped with the serial data receiving device, wherein the receiving device controls the transfer of the serial data.

Abstract: An electronic device for transferring data between a serial port and a memory of a CPU is provided having a plurality of data registers for transferring data between said serial port and said memory in response to a first set of control signals, a data bus connected to said registers and said memory for passing data to and from said memory in response to a portion of said first set of control signals, first control circuitry for generating said first set of control signals and for generating at least one interrupt to said CPU, at least one control register connected to said first control circuitry for providing mode control information to said first control circuitry, a plurality of address registers for storing data address, at least one address generator connected to said address registers for automatically generating addresses in response to a second set of control signals, an address bus connected to said address registers, and second control circuitry connected to said address generator, a portion of sai

Abstract: A system for eliminating access time in CD-ROM based interactive video applications. A CD-ROM disc is formatted with multiple interleaved animation sequences. During playback, a user is able to select a sequence as the current sequence. Only those frames corresponding to the current sequence are displayed while other frames are dropped. The interleaved pattern of frames allows multiple sequences to be available from the CD-ROM drive without requiring repositioning of the CD-ROM drive's read head thereby eliminating access time. Specific patterns of interleaving that advantageously improve interactivity of an interactive production are described. A frame buffering implementation is described.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.

Abstract: A service utilization information collection apparatus in a system including a plurality of computers interconnected through a network acquires names of computers which utilize services provided by a server machine and service utilization status from any one of the computers in the system, and includes a user command which may be executed in any one of the computers, and a service monitor and a local service monitor. A service to be monitored and a name of the server which provides the service are inputted to the user command which is sent to the service monitor. The service monitor issues a service utilization information collection request to the local service monitor operating on each of the computers. The service utilization information collected by the local service monitor is sent to the user through the service monitor and the user command.

Abstract: An n-byte buffer is able to store n bytes of data. A interrupt request signal generating circuit interrupts the processor of the peripheral apparatus after receiving the nth byte of the data. Accordingly, only one interrupt operation is needed to receive and input n bytes of data. Consequently, the number of interrupt operations is reduced and the data processing speed is improved.

Abstract: A system which uses an arrangement of FIFO buffers which include circuitry to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer. Each FIFO buffer includes a flow control register which stores a value which indicates the amount of space available in the FIFO to which data may be written. In order to allow for situations in which data is available at a FIFO buffer which cannot be immediately utilized for some reason, an overflow storage area is provided for storing data transferred to the FIFO buffer in excess of the number of stages of the FIFO circuit which are available to store data. The flow control circuitry also includes circuitry for assuring that data which is placed in the overflow storage area is handled in the appropriate sequence.

Abstract: A serial interface includes a first port capable of transmitting and receiving data in a serial fashion. A first p-channel transistor is coupled to the a first port. A first n-channel transistor is coupled to the a first port. A first control circuit is coupled to the first p-channel transistor for disabling the first p-channel transistor so that the first port can operate in a first serial data transfer mode wherein the first n-channel transistor operates in an open-drain fashion. A second port is capable of transmitting and receiving a clock signal which is used to control data transfer through the first port. A second p-channel transistor is coupled to the a second port. A second n-channel transistor is coupled to the a second port. A second control circuit is coupled to the second p-channel transistor for disabling the second p-channel transistor so that the second port can operate in the first serial data transfer mode wherein the second n-channel transistor operates in an open-drain fashion.

Abstract: An interface circuit used to connect industry standard PCMCIA (Personal Computer Memory Card International Association) cards to a personal computer via a standard parallel printer port. The invention utilizes a mechanism which enables direct access to each I/O or memory address on a PCMCIA card independently. This is done by transferring an I/O or memory address in a PCMCIA card via the data lines of the parallel port, decoding this address, and providing the decoded address to the PCMCIA card. As a result, application software which accesses the PCMCIA card can run without modification. All that is needed is add-on code which captures and re-routes accesses generated by the application software to the parallel port. This add-on code captures the I/O instructions targeted at the I/O device associated with the PCMCIA card and replaces them with sequences of instructions routed through the parallel port.

Abstract: In a computer and a printer connected through a parallel interface called Centronics interface, after determining whether or not bidirectional transmission of data with the printer is possible, a printer setting device displays a message indicating the status or settings of the printer. An operator selects and sets the desired printer settings while viewing this display. On the other hand, when bidirectional transmission with the printer is not possible, predetermined default settings are set to the printer and the device displays the default settings. Therefore, the printer setting device can operate even when support for bidirectional transmission of data is not provided. Further, regardless of whether bidirectional transmission of data is possible, the operator can freely change the settings of the printer so that the functions of the printer can be more fully utilized.

Abstract: A system and method for disabling and re-enabling PCI-compliant devices in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a PCI/Host bridge coupled to the host bus, one or more PCI-compliant devices, a PCI bus coupling the PCI/Host bridge and the PCI-compliant devices, and a device, typically in the form of a digital gate, for selectively disabling or re-enabling one or more of the PCI-compliant devices. The disclosed method operates in connection with a computer system having a CPU, a PCI/Host bridge coupled to the CPU and capable of sending an IDSEL signal to the IDSEL input pin of a target PCI-compliant device when attempting a read or write operation on the target PCI-compliant device, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PCI-compliant device.

Abstract: A method and system for providing access to independent network resources. At system logon, logon data is stored in memory of a client computer. When a server is accessed, server authentication data is stored in a cache. System logon data and authorization data can be applied to access an independent server resource without requiring user interaction.

Abstract: The present invention relates to a method and to a computer system arrangement for producing a dialogue between a central computer unit and at least one user unit. The user unit includes at least one display means and a memory means and can be connected to the central computer unit. The central computer unit includes a central memory means in which there is stored a software part, called the dialogue part, which is intended for data processing requested by the user unit. Information concerning the text and/or picture for presentation on the display means is pre-stored in the user unit memory means and separate user units may be of different types. The information transmitted from the central computer unit to the user unit during a dialogue session includes at least one first identifier which corresponds to a message to be transmitted, wherein the first identifier points out a presentation object which corresponds to the message in the user unit memory means.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: Apparatus for emulating input/output devices on an ISA bus using input/output devices on a local bus which includes circuitry for snooping on the bus to capture commands sent to input/output devices the functions of which are to be emulated, circuitry for storing those commands, circuitry for generating new commands in response to the commands which are stored, and circuitry for generating output signals in response to the new commands which output signals replace the output signals produced by the input/output devices on an ISA bus.

Abstract: It is an object of the present invention to restrict EMI radiation at a specific frequency by inserting a delay time that is effective for that frequency. The feature of the present invention is to provide a delay generator that can selectively alter delay times. The delay generator comprises: delay means, which is connected to a plurality of data input lines, and which has a plurality of delay paths for the generation of a plurality of alternative delay times; a register for storing a digital value of pre-determined bit; and selection means for selecting one of the delay paths in consonance with the digital value and for providing the selected delay path for the signal lines.

Abstract: A difference recording apparatus includes a log comparator, a processing unit, a recording unit, and a log update section. The log comparator detects a log difference by using a classification key in a log of input data. The processing unit restores the log by using difference data from the log comparator. The recording unit records the log restored by the processing unit. The log update section limits recording of a log of identical data in the recording unit within a unit time on the basis of the presence/absence of a difference detected by the log comparator and an upper limit of log acquisition.

Abstract: In a typical storage medium, such as a magnetic hard disk, there is a file allocation table (FAT) stored thereon which is referenced each time the medium is accessed. Many data processing mechanisms rely on the existence of this FAT for accessing the medium. However, some storage media, such as CD-ROM's, do not have FAT's stored thereon. In order to properly interface FAT reliant data processing mechanisms with storage media having no FAT, file storage information is first obtained from the storage medium. Then, using this file storage information, a FAT having a format compatible with the data processing mechanisms is generated. Information from the FAT is provided to the mechanisms and, using this FAT information, the mechanisms can access information on the storage medium. Thus, even though the storage medium has no FAT, it is still accessible by FAT reliant data processing mechanisms.

Abstract: An airline ticket printer includes a magnetic reading and writing station that has a read/write head for recording information on, or reproducing information from, a magnetic stripe carried on the ticket. The ticket is driven past the read/write head by a drive mechanism that contacts the ticket at a substantial distance from the read/write head so that the magnetic stripe is free to flex independently of the portion of the ticket that is in contact with the drive mechanism. More satisfactory contact between the read/write head and the magnetic stripe is thereby achieved.The printer's control system includes a printer electronics board and one or more single-slot PC/AT (ISA bus) microcomputers that are plugged into respective slots of a mother board.

Abstract: A bus interface unit for passing data between an I/O bus and a system bus in a dual bus computer system is provided. The bus interface unit has incorporated therein an address listing and compare function to determine whether a requesting device on the I/O bus is to read data from or write data to an address on the system bus. If so, the bus interface unit allows passing of the data therethrough. If not, the system bus is relinquished and the requesting device writes to the address on the I/O bus. Also, compare logic is incorporated in the bus interface unit which decodes system bus addresses originated from a system bus controller such as the DMA, to determine whether the destination of the transfer is to system memory or the I/O bus.