Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

Abstract: An illustrative method includes determining whether a virtual storage volume is successfully mounted to a mount path associated with a compute node, the mount path being marked as read-only, marking, if the determining includes determining that the virtual storage volume is successfully mounted to the mount path, the mount path as writable, and maintaining, if the determining includes determining that the virtual storage volume is unsuccessfully mounted to the mount path, the mount path as read-only.

Abstract: To generate sequential addresses when multiple integrated circuit (IC) devices are accessing a memory region, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token includes a data increment value for the memory region. When a device receives the address token, a memory write address is determined based on the data increment value and a base address corresponding to the memory region for the current write cycle. The IC device can perform a write operation using the memory write address if the device has data to write. The data increment value of the address token is then updated based on the number of data units being written in the current write cycle to the memory region by the IC device, and the updated address token is transmitted to the next IC device of the ring topology.

Abstract: A memory controller includes a map buffer and a map update controller. The map buffer includes storage areas that respectively correspond to one or more indices. The map update controller stores metadata in a storage area corresponding to a target index among the one or more indices, and updates the metadata based on an update of mapping data for a first logical address. The metadata includes history information of a physical address mapped to the first logical address.

Abstract: Techniques are disclosed which allow a secondary storage system to provide data to non-production workloads in conjunction with performing data backup and protection tasks. As disclosed, a secondary storage system exposes backup data stored by the secondary storage system to other workloads, such as test and development applications, data analytics, etc. These non-production workloads can run at the same time the secondary storage system provides backup services to a primary storage system. This consolidation eliminates the need for an enterprise to deploy separate storage clusters for analytics, test and development applications, etc. and eliminates unnecessary copies of data.

Abstract: A computer-implemented method according to one aspect includes receiving a request to perform a transaction in persistent memory; determining a correlation between volatile memory address locations in a volatile transaction cache and persistent memory locations in the persistent memory; performing the transaction within the volatile memory address locations of the volatile transaction cache; identifying modified volatile memory address locations in the volatile transaction cache that have been written during the transaction; logging, within the persistent memory, data within the modified volatile memory address locations; copying the data within the modified volatile memory address locations to corresponding persistent memory locations in the persistent memory, utilizing the determined correlation; and removing the logged data from the persistent memory, in response to determining that the copying has completed.

Abstract: In a multi-node storage system, a node's capacity has an upper limit, and capacities provided by nodes are smaller than a capacity of a global pool. A volume having a capacity larger than the capacity of one node is created by the node. A write error occurs when an amount of data larger than the capacity of the node is written. A storage system reduces the frequency of such a write error. A global pool is based on a plurality of local pools of a plurality of storage nodes that constitute a node group. In any of the storage nodes, a capacity relationship is maintained where a used capacity of a volume created by the storage node is equal to or less than an available capacity of a local pool of the storage node. A storage management unit manages the node group and selects the storage node.

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

Abstract: A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.

Abstract: Data traffic comprising data packets communicated between a memory sub-system and a host system is monitored by a processing device at the memory sub-system. Data packets are classified according to packet type. Log data comprising a frequency and latency information associated with each packet type is generated. The log data is stored in a memory component of the memory sub-system.

Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.

Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

Abstract: Methods, systems, and devices for clock domain crossing queue are described. A memory sub-system can generate a namespace map having a set of namespace blocks associated with a memory sub-system. The namespace blocks can include one or more logical block addresses associated with the memory sub-system. One namespace block of the set of namespace blocks can include an indication that can indicate that the namespace block and each namespace block following the namespace block are available for mapping. The memory sub-system can receive a request to create a namespace and sequentially map one or more available namespace blocks to the namespace according to the ordering of the namespace map, including the namespace block with the indication.

Abstract: Various embodiments disclosed herein are related to a non-transitory computer readable storage medium. In some embodiments, the medium includes instructions stored thereon that, when executed by a processor, cause the processor to send an indication of a first storage location to a destination host. In some embodiments, the first storage location includes content that is swapped out from a memory location in a source host. In some embodiments, the indication includes one or more of a logical address and a first physical address. In some embodiments, the medium includes instructions stored thereon that, when executed by a processor, cause the processor to map the logical address of the first storage location to a second physical address of a second storage location. In some embodiments, the destination host accesses the content of the first storage location.

Abstract: A storage control system maintains a write cache in a non-volatile memory device of primary memory of a storage node. The write cache comprises a cyclic buffer and pointers to manage the write cache and track a tail location and head location of the write cache. The storage control system receives a write request from a host system, which comprises a data item to be written to primary storage. The received data item is written together with an associated metadata item at the head location of the write cache. The items in the write cache are arranged in a cyclic write order from the tail location to the head location. The storage control system sends an acknowledgment to the host system that the data item is successfully written to the primary storage, in response to the received data item and the associated metadata item being stored in the write cache.

Abstract: Embodiments of the present disclosure relate to cache memory management. Based on anticipated input/output (I/O) workloads, at least one or more of: sizes of one or more mirrored and un-mirrored caches of global memory and their respective cache slot pools are dynamically balanced. Each of the mirrored/unmirrored caches can be segmented into one or more cache pools, each having slots of a distinct size. Cache pool can be assigned an amount of the one or more cache slots of the distinct size based on the anticipated I/O workloads. Cache pools can be further assigned the amount of distinctly sized cache slots based on expected service levels (SLs) of a customer. Cache pools can also be assigned the amount of the distinctly sized cache slots based on one or more of predicted I/O request sizes and predicted frequencies of different I/O request sizes of the anticipated I/O workloads.

Abstract: A method to build a persistent memory (PM)-based data storage system without involving a processor (CPU) at storage nodes is disclosed which includes storing data in one or more storage nodes that only include PM and no CPUs, with data stored in PM in form of link lists, accessing data stored in the one or more storage nodes' PM directly by remote compute nodes through a network, maintaining metadata associated with the data by one or more global controllers (metadata servers), upon request by a user to read or write data, the compute nodes contacting the one or more metadata servers to obtain location of data of interest in form of pointers (shortcuts), and the compute nodes sending network requests directly to the one or more storage nodes' PM to locate latest version of data by tracing the link list from the associated shortcut to corresponding tails.