Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

Abstract: A terahertz device includes a terahertz element, a sealing resin, a wiring layer and a frame-shaped member. The terahertz element that performs conversion between terahertz waves and electric energy. The terahertz element has an element front surface and an element back surface spaced apart from each other in a first direction. The sealing resin covers the terahertz element. The wiring layer is electrically connected to the terahertz element. A frame-shaped member is made of a conductive material and arranged around the terahertz element as viewed in the first direction. The frame-shaped member has a reflective surface capable of reflecting the terahertz waves.

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

Abstract: Disclosed herein are approaches for reducing buried channel recess depth using a non-doping ion implant prior to formation of the buried channel. In one approach, a method may include providing an oxide layer over a substrate, performing a non-doping implantation process through the oxide layer to form an amorphous region in the substrate, and forming a photoresist over the oxide layer. The method may further include forming a buried layer in the substrate by implanting the substrate through an opening in the photoresist, and performing an oxidation and dopant drive-in process to the amorphous region and to the buried layer to form a second oxide layer.

Abstract: A method for activating a backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.

Abstract: The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device by which peeling off of a sealing resin and a wire from each other can be practically suppressed are disclosed. The semiconductor device includes a substrate, a main face wire, a semiconductor element that is conductive to the main face wire, a sealing resin having resin side faces directed in a direction crossing a thickness direction, the sealing resin sealing the main face wire and the semiconductor element, a through-wire that is conductive to the main face wire and having an exposed rear face exposed from the substrate, and a column conductor that is conductive to the main face wire and having an exposed side face exposed from the resin side faces. The column conductor is supported from the opposite sides thereof in the thickness direction by the substrate and the sealing resin.

Abstract: A semiconductor package component and a semiconductor package including the same. More particularly, the present disclosure relates to a semiconductor package component for an RF power transistor and a semiconductor package including the same. Further particularly, it relates to a semiconductor package component for an RF power transistor and a semiconductor package including the same, capable of adjusting impedance matching of an RF transistor by connecting a die chip and a lead frame with a wire so that a length of the wire is reduced as much as the protruding height of the base substrate.

Abstract: A method of forming a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A semiconductor substrate is provided, in which a plurality of isolation grooves distributed at intervals are provided in the semiconductor substrate, and each of the isolation grooves includes a top region isolation groove and a bottom region isolation groove. A first protective layer covering the side wall of the top region isolation groove and the top of the semiconductor substrate is formed. Oxidation treatment is performed on the bottom region isolation groove to oxidize a part of the semiconductor substrate close to the bottom region isolation groove to form a second substrate isolation layer. A dielectric layer filling the isolation groove is formed. The first protective layer and the dielectric layer higher than the top of the semiconductor substrate are etched to form an isolation structure.

Abstract: A semiconductor device includes a semiconductor substrate, first and second nitride-based semiconductor layers, S/D electrodes, a gate electrode, and a first passivation layer. The first nitride-based semiconductor layer is disposed over the semiconductor substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a 2DEG region. The S/D electrodes is disposed over the second nitride-based semiconductor layer. The gate electrode is disposed between the S/D electrodes. The first passivation layer is disposed over the second nitride-based semiconductor layer. Edges of the first and second nitride-based semiconductor layers and the first passivation layer collectively form a stepped sidewall over the semiconductor substrate.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

Abstract: A packaging substrate, a packaging structure, an electronic device and a manufacturing method, and pertain to the field of chip packaging technologies. The packaging substrate includes a body including metal cabling. The body includes a first surface, a second surface and a side surface. The side surface is connected to the first surface and second surface. The first surface includes many first connection structures. The second surface includes second connection structures. The side surface includes third connection structures. A part of the first connection structures are connected to the second connection structures by using the metal cabling. The other part of the first connection structures are connected to the third connection structures by using the metal cabling. When the same total quantity of pins need to be disposed, a part of the pins are transferred to the side surface of the body, with less pins at the second surface.

Abstract: The disclosure provides a display device, including a substrate, a plurality of power lines and a pixel define layer. The plurality of power lines disposed on the substrate. The pixel define layer is disposed on the substrate, wherein the pixel define layer includes a first opening region and a second opening region. In a top view, the first opening region is adjacent to the second opening region, the first opening region overlaps a first power line of the plurality of power lines to define a first overlapping area, the second opening region overlaps a second power line of the plurality of power lines to define a second overlapping area, and the first overlapping area is different from the second overlapping area.

Abstract: The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Abstract: A semiconductor device package having stress isolation is provided. The semiconductor device package includes a package substrate and a sensor attached to the package substrate. A first isolation material is formed around a perimeter of the sensor. An encapsulant encapsulates at least a portion of the first isolation material and the package substrate.

Abstract: The present disclosure relates to a molded radiofrequency, ‘RF’, power package. The present disclosure further relates to a method for manufacturing such package. According to example embodiments, weakening structures are provided in the leads to allow the leads to be bent without causing delamination in the body of solidified molding compound.

Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.