Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.

Abstract: A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm?3. A ratio of the chalcogen atoms to the atoms of the background doping is in a range from 1:9 to 9:1.

Abstract: Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.

Abstract: A stretchable substrate including a plurality of islands that are disposed in a planar lattice pattern and spaced apart from each other, and a plurality of bridges that connect two adjacent islands. An aperture is formed between a pair of bridges, which are adjacent and parallel to each other, and the plurality of bridges are capable of stretching and contraction, and the shapes of the islands remain unchanged during the stretching and contraction of the bridges.

Abstract: A method of manufacturing an EL display device having a panel part that comprises a light emitting part in which a plurality of pixels are arrayed, and a thin-film transistor array device to control light emission of the light emitting part. The method includes the following steps: forming the panel part on a substrate, and then forming a sealing layer to cover the panel part. The step of forming the sealing layer is performed by forming a film configuring the sealing layer, with the mask being disposed over base substrate. Mask includes contact part in contact with the base substrate, and edge part disposed over the panel part with a gap between the edge part and the panel part.

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the substrate further comprising a patterned hardmask layer disposed on the multi-material layer, etching the multi-material layer through openings defined by the patterned hardmask layer to expose sidewalls of the first and the second layer of the multi-material layer, and laterally and selectively etching the second layer from the substrate.

Abstract: A thin film transistor is disclosed in the present invention, including a substrate, a gate, an insulating layer, a source, a drain and an active layer. The gate is arranged on the substrate. The insulating layer is arranged on the gate. The source and the drain are arranged on the insulating layer. The active layer is arranged between the source and the drain, and is formed by a bottom layer, an intermediate layer and a top layer stacked together on the insulating layer. The conductivity of the intermediate layer is higher than that of the bottom layer, and the conductivity of the bottom layer is higher than that of the top layer. As such, the disadvantage of low carrier mobility as commonly seen in the conventional thin film transistor is overcome.

Abstract: A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a p-side metal pillar, an n-side metal pillar, and an insulator. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side metal pillar includes a p-side external terminal. The n-side metal pillar includes an n-side external terminal. At least one selected from an area and a planar configuration of the p-side external terminal is different from at least one selected from an area and a planar configuration of the n-side external terminal.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

Abstract: The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion.

Abstract: A memristor includes a first electrode; a second electrode; and a switching layer interposed between the first electrode and the second electrode, wherein the switching layer includes an electrically semiconducting or nominally insulating and weak ionic switching mixed metal oxide phase for forming at least one switching channel in the switching layer. A method of forming the memristor is also provided.

Abstract: In one embodiment, a method includes depositing a CIGS precursor layer onto a substrate, introducing a source-material layer into proximity with the precursor layer, where the source-material layer includes one or more of Cu, In, or Ga, and one or more of S or Se, and annealing the precursor layer in proximity with of the source-material layer, where the annealing is performed in a constrained volume, and where the presence of the source-material layer reduces decomposition of volatile species from the precursor layer during annealing.

Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.

Abstract: A light emitting diode package, a light source module and a backlight unit including the same are provided. A plurality of light emitting diode packages are arranged on a printed circuit board without interference therebetween, by forming lines therein.

Abstract: A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

Abstract: An light emitting diode (LED) module includes a circuit board, a set of LED chips formed on and electrically connected to the circuit board, and an encapsulant arranged on the circuit board and covering the LED chips, a set of first recesses defined in a top surface of the encapsulant.

Abstract: A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion.

Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.