Abstract: The external power supply voltage applied to an external power supply terminal is supplied to an internal stepdown circuit and a switch circuit. The value of the external power supply voltage is detected by an external voltage detecting circuit, and if the value is greater than a predetermined value, the internal stepdown circuit operates, the external power supply voltage is stepped down by the internal stepdown circuit and supplied to an internal circuit as an internal power supply voltage. On the other hand, if the value of the external power supply voltage is smaller than the predetermined value, the internal stepdown circuit does not operate, and instead the switch circuit operates and the external power supply voltage is supplied via the switch circuit to the internal circuit as the internal power supply voltage.

Abstract: In a hysteresis comparator for comparing an input Vin1 with another input Vin2, the comparator comprises a pair of first and second transistors. The gate of the first transistor is supplied with the input Vin1 and the gate of the second transistor is supplied with the input Vin2. Their collectors are connected to a power supply. The emitter of the first transistor is connected to a first current source and the emitter of the second transistor is connected to a second current source. The comparator further comprises a circuit for detecting an emitter voltage difference between the first and second transistors and varying at least one of the first and second current sources. Therefore, the hysteresis width can be determined by the collector current ratio of specific transistors, regardless of the absolute values of their collector currents.

Abstract: There is disclosed a semiconductor device in which the resistance pattern on the semiconductor substrate is formed by the resistance film and the wiring pattern connected to the resistance pattern is formed by the resistance film and the conductive film deposited and formed thereon. Furthermore, a method of manufacturing such a semiconductor device by a photolithographic process is disclosed. In accordance with this method, after the resistance film is formed, a conductive film is formed thereon and the conductive film corresponding to the portion serving as a resistance element is removed. A convex portion may be provided on the insulating substrate, thus to form wiring only on this region or to form wiring only around this region.

Abstract: The present invention provides a P-N-P diamond transistor and a method of manufacture thereof. The transistor comprises a diamond substrate having two p-type semiconducting regions separated by an insulating region with an n-type semi-conducting layer established by chemical vapour deposition. Preferably the p-type regions are obtained by doping with boron and controlling the concentration of nitrogen impurities by the use of nitrogen getters. The n-type layer preferably contains phosphorus.

Abstract: A booster circuit comprises a p-MOS transistor, two n-MOS transistors and a bootstrap capacitor. In the booster circuit, an output signal is charged up to a potential of a power supply through the n-MOS transistors, then is pushed up to a potential higher than that of the power supply by a bootstrap capacitor through the p-MOS transistors. In such a structure, the p-MOS transistor operates as a switching element when pushing up the output signal, so that operation speed is much higher than a conventional booster circuit in which n-MOS transistors are used as switching elements.

Abstract: A dynamic random access memory cell comprises a switching transistor and a storage capacitor formed in a relatively deep trench and having a capacitor electrode projecting over the major surface of the semiconductor substrate, wherein the switching transistor comprises a source/drain region formed along a wall portion defining the relatively deep trench, another source/drain region formed in the major surface portion, a channel region extending partially along a wall portion defining a relatively shallow trench and partially beneath the major surface so that a channel length is prolonged, thereby decreasing an occupation area without any punch-through phenomenon.

Abstract: A semiconductor integrated circuit for obtaining constant voltage characteristics or a current switching function by controlling an output current using a current control element has a DC input terminal, a common input/output terminal, and an output terminal. A junction field effect transistor (JFET) is used as a current control element. The first main electrode (drain) and second main electrode (source) of the JFET are connected to the DC current input terminal and the output terminal, respectively. A DC power is input between the DC input terminal and the common input/output terminal. A power between the output terminal and the common input/output terminal is applied to a load. A maximum current of the JFET is limited to a drain maximum saturation current and a current having a value larger that of the maximum saturation current is not basically supplied to the JFET.

Abstract: The actuator is connected in series between the power supply and the flashing light. It includes a switch which is connected in series between the power supply and the flashing light so that when the switch is closed the light turns on and when the switch is open the light is turned off. A comparator controls the opening and closing of the switch at a frequency determined by an RC timer. Also, the duty cycle of the flashing light is controlled by the timer. A current overload protector lowers the duty cycle of the flashing light as the magnitude of the overload is increased and, in the event of a short circuit, decreases the duty cycle to approximately zero.

Abstract: A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a roughened backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The roughened backside surface helps to reduce package cracking arising from mounting the device to a printed circuit board by reflow solder.

Abstract: A low skew clocking system for VLSI intergrated circuits in which a reference chip, preferably a microprocessor, generates local synchronization signals for the other chips on a common PC board. This reduces the clock skew between the reference chip and all other chips by as much as 50%. Skew between chips is further reduced by using a differential MOS driver responsive to locally generated synchronization signals to generate differential synchronization outputs. Processing speed may be further improved in accordance with the invention by implementing a quadrature clocking scheme using the differential synchronization outputs from the MOS driver whereby the timing delays between the differential quadrature clocking signals are determined by the PC board delays.

Abstract: A flashing light warning apparatus, which includes a voltage source (U), a main gate transformer (HW), a flash tube (R), an ignition device (Z), at least one storage condenser (K), and an electrical switching device (S), can be switched to provide light energy for daytime flashes and nighttime flashes in an uncomplicated, cost effective system which produces dependable light flashes. The night flashes have a light energy such that they can be seen from afar only with night vision apparatus. When the switching device turns off voltage production of the main gate transformer or further transmission of voltage from the at least one storage condenser, the ignition device is coupled to an auxiliary gate transformer (ZW) for carrying out light flash production by means of high frequency ignition voltage produced by the ignition device.

Abstract: In flashing light warning apparatus of a type having a voltage source (U), a main blocking transformer (HW), a flash tube (R), an ignition device (Z), a first and a third storage condenser (K1, K3), and an electrical switching device (S1), a switching path of the first electrical switching apparatus is arranged parallel to the first storage condenser, the third storage condenser and the ignition device are coupled to an auxiliary blocking transformer (ZW), and the first switching device can be switched by a control device (B). Such a flashing light warning apparatus can be produced in an uncomplicated, cost effective manner, to provide light energy which can be changed during operation to provide a day flash and at least one type of night flash. The night flash is at such a level that its output can be recognized from afar only by night vision apparatus.

Abstract: An improved working point adjusting circuit for a single power amplifier having multiple output circuits. When this simple circuit is connected to a Class B transistor power amplifier to support two or more output channels or speakers, it adjusts the working point of the transistors in the output circuit of the power amplifier to the linear portion of the current-voltage characteristics of the transistor so the amplifier works in the level of a Class A amplifier. It provides many significant advantages including (1) much higher energy efficiency on output transistors; (2) much less signal distortion on loaded speakers; (3) simple circuitry for increased reliability; (4) low component count for reduced costs; and (5) individualized adjustment for each output channels which eliminates the different effect caused by the very fine differences between the multiple loaded output devices such as loudspeakers.

Abstract: An amplifier circuit is provided with first to third amplifying stages, a constant current source and a feedback circuit. The minimum value of current flowing through the output-stage transistor of the amplifier circuit is limited chiefly by the action of the feedback circuit. This prevents the output-stage transistor from becoming cut off, even when an excessive input signal is applied and high-speed circuit operation is realized. Also, a maximum value of current flowing through the output-stage transistor is limited so as to prevent an excessive output current. This will realize protection of the amplifier circuit against overcurrent.

Abstract: The present invention relates to an increased operating voltage MOS semiconductor device. The device has a channel forming area between a source and extended drain area, a gate insulating film over the channel forming area and the drain area with a thicker portion over the drain area, and a gate electrode over the gate insulating film, thereby preventing an excess field concentration from existing in the extended drain region. The field concentration may be further reduced by forming a relaxation area underneath the juncture between the thick and thin portions of the gate insulating film below the surface of the drain area.

Abstract: A circuit to selectively process dip switches onto bus lines in a computer or device utilizing digital logic circuits wherein the dip switches are operably connected to a changeable source of digital signals so that upon command at desired times, the output of the dip switches connected to the bus lines may be reversed. Such a circuit consists of connecting the dip switches on one side to the bus lines and the other side through a current limiting resistor to the output of a logic circuit such as a NAND gate or other circuit which constantly outputs a digital signal. The input then to this logic circuit may be changed as desired to reverse the logic circuit output and thus the output of the dip switches. If desired, in place of the NAND gate output, the current limiting resistor may be grounded or connected to digital "1" in which case a constant digital signal is outputted to the bus lines upon dip switch closure.

Abstract: The present invention minimizes the noise voltage associated with the switching of output driver transistors of integrated cicruits caused by the rapid change in value of the current, expressed by the term di/dt, from the load into the driver transistors through the package leads. The present invention uses a programmable coarse current control (CCC) circuit and a programmable fine current control (FCC) circuit that control the pull-down output transistors. The FCC creates two time periods, after which it prevents the CCC from controlling an output pull-down transistor. The FCC and the CCC are used to reduce the di/dt dependent voltage noise by controlling the slope and the shape of the output voltage pull-down characteristics.

Abstract: A pulse driver circuit for providing very high frequency pulses with fast rise time to neon or gas discharge lamps to thereby produce higher optical output than is possible using conventional drivers. Gas discharge lamps have at least two states of operation. One is the application of breakover voltage to initiate gas ionization which may be called the preionization state. The second state is known as the breakdown condition which is when the gas in the lamp has ionized and is producing the optical output. The pulse driver, starts the ionization at a relatively low breakover voltage because of its fast rise time. The pulse driver comprises an astable oscillator, the output of which passes through a pulse width capacitor. The generated pulse train drives a power driver transistor which causes current to flow through a transformer causing a voltage to be applied to a lamp.

Abstract: A V.sub.OH clamp circuit reduces propagation delay time TP.sub.HL and reduces ground bounce noise in TTL output buffer circuits. First and second band gap bias generators (BG1,BG2) coupled in series provide a substantially stable clamp reference voltage level (V.sub.R) over a specified range of operating temperatures. The clamp reference voltage level (V.sub.R) is referenced to the low potential power rail (GND). Voltage drop components (D32,QC) of the Y.sub.OH clamp circuit couple the reference voltage level (V.sub.R) through the voltage drop components (D32,QC) to an internal node, namely the base node (BDAR) of the pullup Darlington configuration transistor pair (Q12A,Q12B), The V.sub.OH clamp circuit clamps the high potential level output signal (V.sub.OH) at a maximum voltage level (V.sub.OHMAX) less than the high potential level power rail (V.sub.cc), and referenced to the clamp reference voltage level (V.sub.R).

Abstract: A Via-Less Two-Metal Tape-Automated Bonding System [100] for providing an interface to a device having a plurality of closely spaced leads is disclosed. The preferred embodiment of the invention comprises a dielectric film [102]that bears a pattern of conductive signal traces [104] on one side [102b] of the film [102] that match the leads of an integrated circuit that is fastened to the center of the rectangular TAB frame. The side [102a] of the film which is opposite from the side [102b] bearing the signal traces [104] has a ground plane [105] attached to it that controls the impedance characteristics of the conductive elements of the TAB frame. In previous TAB designs, the ground plane [105] is connected to the chip through a ground lead [106] that is coupled to the ground plane by a via that passes through the dielectic film in a direction that is perpendicular to the two planar axes of the film.