Abstract: The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: A switch includes a housing forming a cavity, a first electrode, and a second electrode. The first electrode has an inner surface having a generally circular cross-section perpendicular to an axis and extending along the cavity in a first direction along the axis, forming a hollow tube. The second electrode has a generally circular cross-section perpendicular to the axis and extending into the cavity in a second direction along the axis. The second electrode extends at least partially into the hollow tube formed by the first electrode.

Abstract: A high frequency electronic ballast for a lamp (20) includes an LC filter (5) and a voltage doubler circuit (8) coupling AC input terminals (1, 2) to DC input terminals (13, 14) of a half bridge DC/AC converter circuit (15). One end of the lamp is coupled to the capacitors (16, 17) of the voltage doubler circuit via a coupling capacitor (21) and the voltage doubler diodes (11, 12) and the other end of the lamp is coupled via an LC circuit (24, 25 and 26) to a junction point (22) between first and second switching transistors (18, 19) of the half bridge circuit. A capacitor including the lamp and the LC circuit so that the half bridge circuit will oscillate at a high frequency. Energy is fed back to the voltage doubler capacitors via the coupling capacitor and the LC circuit to maintain the capacitor voltage above the peak of the AC supply voltage and thereby provide a circuit with a high power factor and low harmonic line current.

Abstract: A control system for reducing power used by an inductive lighting installation, usually plural fluorescent lamps and a ballast, includes an A.C. power input circuit to the installation with a signal-actuated, normally-closed primary switch in series in the circuit; a signal-actuated normally-open secondary switch is in shunt with the load. The two switches are actuated substantially simultaneously in each half-cycle of the A.C. power input, once for power reduction for a time interval T1-T2 and once for harmonic distortion reduction for a time T3-T4 that encompasses each A.C. power zero-crossing time TX. The control system has N different timing programs for times T1-T2 and T3-T4, each program corresponding to one type of ballast. In each program times T3 and T4 are constant; only the times T1 and T2 are varied for a series of successively greater power reductions; the maximum power reduction may be as much as 30 to 40 percent.

Abstract: A flat type fluorescent lamp device is constituted by two transparent glass plates assembled and sealed together thereby forming a glass plate assembly, a discharge channel formed in a serpentine form by a groove on at least one of the two transparent glass plates with the inner surface of the groove carrying a fluorescent film. A pair of electrodes are provided, electrode each at each end of the discharge channel, a light diffuser provided on the front surface of the glass plate assembly and a light reflector is provided at the back surface of the glass plate assembly. In one aspect of the invention, at least another electrode is provided between the two electrodes thereby dividing the discharge channel into a plurality of individual discharge channels, in which case it is possible to ensure that all of the individual channels have the same electric characteristics and can be caused to be lit in parallel by a single power source.

Abstract: A novel double diffused complementary MOS (DCMOS) logic family is disclosed which allows greater tolerance to total dose gamma radiation. The logic family may be fabricated in conventional power BiCMOS IC technology in which complementary power DMOS output devices and Bi-polar transistors are integrated with high performance complementary MOS devices to perform both digital and analog functions. The incorporation is achieved without the additional masks or process modifications normally required for improving radiation tolerance.

Abstract: An improved display bias arrangement is provided using a DC filament voltage in conjunction with stepped grid voltages to maintain even illumination. In a VF display there is a directly heated cathode (filament), an anode and a grid. If a DC filament voltage is used, one end of the cathode will be at different potential than the other, thus resulting in a variation in anode-to-cathode potential across the display. This varying potential causes electrons to hit the anode with varying speed, causing a variation in display intensity. In this invention, the cathode (filament) is supplied with a DC voltage and the grid of each segment is supplied with a different voltage, thereby equalizing the anode-to-cathode potential for each display digit. In a first embodiment, resistor networks are used to equalize the anode-to-cathode voltages. In a second embodiment, diode networks are used to equalize the anode-to-cathode voltages.

Abstract: A dimming system for a discharge lamp has a magnetic regulator with first, second and third windings linked by a magnetic core, the first winding being connectable to a source of alternating current. The second winding and a starting circuit are connected to the lamp for lighting the lamp. The third winding is tapped and has a ballast capacitor connected across the winding. An inductive reactor and relay contact set are connected in series between one end of the third winding and the tap so that when the contact set closes, the reactor stores energy from the source and reduces the power to the lamp, abruptly reducing its light output. A motion-responsive detector is used to energize the relay. With a normally closed contact set, the lamp is dimmed until a moving person is detected, opening the contact set and increasing the lamp light output. Multiple lamps can be controlled simultaneously.

Abstract: Counting and division circuits include an input differential stage connected to a cross-coupled differential stage. The input stage includes first and second IGFETS whose gate electrodes are respectively connected to first and second inputs, whose drains are respectively connected to first and second outputs, and whose sources are connected to the drain of a third IGFET whose source is grounded. The cross-coupled stage includes fourth and fifth IGFETs which are cross-coupled in that the gate of the fourth IGFET and the drain of the fifth IGFET are directly connected to the first output and the gate of the fifth IGFET and the drain of the fourth IGFET are directly connected to the second output. The sources of the fourth and fifth IGFETs are connected in common to the drain of a sixth IGFET whose source is grounded.

Abstract: An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems.

Abstract: An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.

Abstract: A method and apparatus for high power pulse modulation which includes a high voltage supply to provide a high voltage input signal, and a drive channel, rise channel, fall channel, and dump channel. A timing system controls the switching of the drive channel, rise channel, fall channel, and dump channel to modulate the high voltage input signal to produce an output signal. Each channel comprises a channel logic input, buffer amplifier, alternating current (AC) coupler, isolation pulse transformer, current limiter, and switch to provide the pulse modulation. Power MOSFETs can be used as switches in the four channels.

Abstract: A fluorescent lamp power control having an input conditioning section, a lamp driver section, and a power command interface and control section to control power to fluorescent lamps. An external power command input is compared to an internally generated, computed power level and an electronic preregulator is controlled to regulate amp power. The preregulator output voltage and lamp driver current are multiplied to obtain a signal indicative of lamp power. A power command interface isolates the external power command input. Fluorescent lamp dimming is achieved by reducing the external power command input signal, reducing the power delivered to the fluorescent lamps.

Abstract: An address transition detection circuit which uses fast inverters in a delay line, avoiding filtering of input pulses and providing significant threshold voltage margin for the input address signal. A pair of gates connected to various points of the delay line detect at at least one point the presence of an address transition passing along the delay line.

Abstract: A carrier tape includes an insulating film supporting a plurality of leads. The film has a center device hole for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the center device hole, a lead supporting portion positioned between the center device hole and the outer lead holes, and a link portion positioned between a pair of adjacent outer lead holes and connected to the lead supporting portion for directing the flow of molten resin during encapsulation of the semiconductor chip. The link portion includes an opening or recess. The plurality of leads of the carrier tape are supported on the lead supporting of the film, with one end portion of each lead projecting into the center device hole of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the center device hole, and the leads are electrically connected to respective electrodes of the semiconductor chip.

Abstract: Composition and solder interconnection structure for its use, wherein the gap created by solder connections between a carrier substrate and a semiconductor chip device mounted thereon is filled with the solvent free formulation obtained by curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof, polyol, and filler which is substantially free of alpha particle emissions.

Abstract: Disclosure herein is an interface circuit for a semiconductor memory device, which is so structured that, when a control signal (VBC) is supplied to a control signal input end, a transistor (2) first enters a conducting state to supply a supply voltage to a semiconductor memory device (1) and thereafter bus control means (7, 8) is brought into a conducting state by a control signal delayed by a delay circuit (22), to supply bus signals (ADD', CTD' and DTS') to the semiconductor memory device.

Abstract: An isolator for isolating semiconductor devices, components of an integrated circuit, on a semiconductor substrate, wherein the isolator is delimited by walls of a trench formed on a top surface of the semiconductor substrate, and the trench is filled with a silicon oxide layer deposited by a chemical vapor deposition method. A small ditch created in the middle of a top surface of the silicon oxide layer in the trench is filled with silicon, and at least a top surface of the silicon is thermally oxidized to form another silicon oxide layer.

Abstract: A limiting circuit comprises a comparator (B), which makes a comparison between the output voltage (Vc) of a power device and a predetermined reference voltage (Vrif). In the case wherein the output voltage is just below the reference voltage, the comparator supplies a current to the load (L) suitable for preventing the output voltage from falling further below the reference voltage.

Abstract: A bootstrap circuit with a word line of a semiconductor memory device comprises a bootstrap unit having a bootstrap capacitor coupled at one electrode thereof to an output node and supplied from an input node with an input signal, and responsive to a booting signal of a power voltage level supplied to the other electrode of the bootstrap capacitor for bootstrapping an output voltage at the output node over the power voltage to a first predetermined level in cooperation with a load capacitor; a constant voltage source operative to produce a second predetermined voltage level higher than the low voltage level and lower than the booting signal; and a switching unit operative to supply the booting signal to the other electrode in the presence of the input signal and to feed the second predetermined voltage level to the other electrode in the absence of the input signal, wherein the other electrode of the bootstrap capacitor varies the voltage level between the power voltage level and the second predetermined volt