Patents Examined by Raj R Gupta
  • Patent number: 10173887
    Abstract: A device with an out-of-plane electrode includes a device layer positioned above a handle layer, a first electrode defined within the device layer, a cap layer having a first cap layer portion spaced apart from an upper surface of the device layer by a gap, and having an etch stop perimeter defining portion defining a lateral edge of the gap, and an out-of-plane electrode defined within the first cap layer portion by a spacer.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 8, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Andrew Graham, Gary Yama, Gary O'Brien
  • Patent number: 10170715
    Abstract: The invention relates to a method for producing a vertical organic field-effect transistor, in which a vertical organic field-effect transistor with a layer arrangement is produced on a substrate, said layer arrangement including transistor electrodes, namely a first electrode (23; 24), a second electrode (23; 24) and a third electrode (32), electrically insulating layers (25; 34) and an organic semiconductor layer (28). In addition, a vertical organic field-effect transistor is provided, which includes a layer arrangement with transistor electrodes on a substrate (21).
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Novaled GmbH
    Inventors: Hans Kleemann, Gregor Schwartz
  • Patent number: 10162335
    Abstract: A numerical controller includes a neighboring point search function that moves a tool controlled by a moving axis and a rotation axis onto a machining path directed by a machining program within the range of a neighboring point distance from a current position of the tool. When searching the neighboring point, the numerical controller determines a neighboring point with consideration for both a tool center point position and a tool attitude. By employing this search method, even when a plurality of block start points are present in the neighboring point distance from the current tool position, a block start point of the block originally desired to be restarted can be determined as a neighboring point.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 25, 2018
    Assignee: FANUC Corporation
    Inventors: Shintarou Zeniya, Takeshi Mochida
  • Patent number: 10163909
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
  • Patent number: 10141339
    Abstract: Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10141324
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Patent number: 10141393
    Abstract: Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 27, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ramsbey, Unsoon Kim, Shenqing Fang, Chun Chen, Kuo Tung Chang
  • Patent number: 10133256
    Abstract: An information processing apparatus includes a processor and a memory. The memory stores three-dimensional data describing a real device including an object, a source of an acting factor that acts on the object and causes a detectable change at the object, and a detector that detects the change in a specified detection range. The processor produces a virtual device that represents the real device in a virtual space, based on the three-dimensional data in the memory. With this virtual device, the processor simulates the change caused by the acting factor, and calculates a region of the object in which the simulated change satisfies a specified condition.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Fumiyuki Takahashi, Tetsuo Koezuka
  • Patent number: 10134762
    Abstract: Embedded security circuits formed by directed self-assembly and methods for creating the same are provided herein. An example integrated circuit includes a set of one or more fin field effect transistor devices unrelated to one or more security devices of the integrated circuit; and an embedded security circuit structure comprising an array of fin field effect transistor devices related to the one or more security devices of the integrated circuit, wherein the array comprises a combination of (i) one or more fin field effect transistor devices with unbroken fin channels and (ii) one or more fin field effect transistor devices with broken fin channels, and wherein the combination forms a distinct code to be associated with the integrated circuit.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10126731
    Abstract: The present invention relates to a height-adjustable table (1) height-adjusting arrangement (100) for adjusting the height of the table (1), wherein the height-adjusting arrangement (100) comprises at least one leg, each leg having an inner tubular member (112) and an outer tubular member (113) arranged for telescopic movement relative to each other, and a linear actuator (114) coupled to said tubular members (112, 113) and which is configured to provide the telescopic movement between the tubular members (112, 113), and an electric motor connected to the linear actuator (114) and configured to operate the linear actuator for providing telescopic movement between the tubular members. The height-adjusting arrangement (100) further comprises an eye detection unit arranged to detect the position of a user's eyes. The height-adjusting arrangement (100) is configured for control of the height of the height-adjustable table (1) based on the detected position of a user's eyes.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 13, 2018
    Assignee: KIH-utveckling AB
    Inventor: Robert Lindström
  • Patent number: 10128206
    Abstract: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Lin, Ming-Da Cheng, Wen-Hsiung Lu, Meng-Wei Chou, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 10121665
    Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chi Dong Nguyen, Klaus Hempel
  • Patent number: 10103151
    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Ting, Kuo-Ching Huang
  • Patent number: 10094922
    Abstract: A position location system and method, the system including: an infrared (IR) transmitter, a first and a second ultrasound (US) transmitter, the first and a second US transmitters arranged at respective predetermined distances from a reference plane, an IR receiver configured to receive an IR signal from the IR transmitter, a US receiver configured to receive a first US signal from the first US transmitter and a second US signal from the second US transmitter; and a processor coupled to a memory and further coupled to the IR receiver and the US receiver, the processor configured to detect: a time of flight (ToF) of the first US signal from the first US transmitter to the US receiver; and a ToF of the second US signal from the second US transmitter to the US receiver.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 9, 2018
    Assignee: CENTRAK, INC.
    Inventor: Israel Amir
  • Patent number: 10095215
    Abstract: A thermal displacement correction apparatus for a machine tool first determines the coefficient k in E=a+k|F| where F is a thermal displacement correction amount and E is an adjustment value (first step). Next, in actual processing, a is set if a has not been set yet (second step). After a and the coefficient k are determined in advance, thermal displacement correction unit is enabled and an operation of a machining program is started. The thermal displacement correction amount F is calculated, the adjustment value E is calculated based on E=a+k|F|, a thermal displacement correction amount F? after adjustment (=E×F) is calculated, and F? is sent to the thermal displacement correction unit.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 9, 2018
    Assignee: FANUC CORPORATION
    Inventor: Xiaoguang Qi
  • Patent number: 10090326
    Abstract: The embodiments of the present invention provide a flexible display substrate and a manufacturing method thereof, as well as a flexible display device, which relate to the technical field of display, and can avoid the performance of the thin film transistor from being influenced by light energy when a flexible substrate is striped from a carrying substrate. The method for manufacturing the flexible display substrate may comprise: forming a flexible substrate on a carrying substrate; forming a first buffer layer on the flexible substrate; forming a plurality of display elements on the first buffer layer, each of the plurality of display elements comprising a thin film transistor and an electrode structure, the thin film transistor comprising a metal oxide semiconductor active layer; stripping the flexible substrate from the carrying substrate, wherein the method further comprises: forming a light absorbing layer before the plurality of display elements are formed.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 2, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jing Yang
  • Patent number: 10073481
    Abstract: Representative implementations of devices and techniques provide local and/or remote control for an appliance. A load control device includes local controls and also includes communication components for remote operations. In one implementation, the load control device is configurable for use with a variety of appliances based on interchangeable sleeves that adapt the load control device to power leads having different configurations.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 11, 2018
    Inventors: Patrick Reed, Joerg Wagner, Corey Wagner
  • Patent number: 10062710
    Abstract: Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Guan Huei See, Rui Tze Toh, Shaoqiang Zhang, Purakh Raj Verma
  • Patent number: 10062786
    Abstract: A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyun Kim, Ho-Young Kim, Se-Jung Park, Bo-Un Yoon
  • Patent number: 10050141
    Abstract: A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. Spacers are formed directly above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed directly on a top surface of the vertical channel fin, between the spacers.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang