Patents Examined by Ramamohan Rao Paladugu
  • Patent number: 5525540
    Abstract: In a method for manufacturing a silicon layer, a silicon layer is grown simultaneously with doping impurities into the silicon layer. Then, an impurity diffusion preventing layer is grown by interrupting this silicon layer growing step at least one time.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: June 11, 1996
    Assignee: NEC Corporation
    Inventors: Masanobu Zenke, Fumiki Aisou
  • Patent number: 5525539
    Abstract: An infrared LED can function efficiently as both an emitter and a detector at a common wavelength without undesirable characteristics found in avalanche diodes. The LED comprises a graded-bandgap Ga.sub.1-x Al.sub.x As semiconductor material with two semiconductive regions that form a p-n junction. The value of x (the amount of aluminum in the semiconductive material Ga.sub.1-x Al.sub.x As) is varied monotonically as the material is grown so that x decreases monotonically from a value greater than approximately 0.08 at the diode surface on the N side of the p-n junction to a value not less than zero at the diode surface on the P side of the junction. The value of x at the p-n junction is greater than 0 and less than approximately 0.08 as a result of a high initial growth temperature of at least about 930 degrees Celsius.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: June 11, 1996
    Assignee: Opto Diode Corporation
    Inventor: James C. Kim
  • Patent number: 5525537
    Abstract: The invention relates to a composite structure for electronic components comprising a growth substrate, an intermediate layer having substantially a crystallographic lattice structure arranged on the growth substrate, and a diamond layer applied on top of the intermediate layer, and to a process for producing a composite structure of this type. In order to obtain a diamond layer of highest quality, the intermediate layer has substantially a zinc blende or diamond or a calcium fluoride structure, in which at the outset of the intermediate layer the difference between the lattice constant of the intermediate layer and the lattice constant of the growth substrate, relative to the lattice constant of the growth substrate, is less than 20%, in particular less than 10%, and in which at the transition from the intermediate layer to the diamond layer for the lattice constant of the intermediate layer and the lattice constant of the diamond layer the value of the expression.vertline.(n*a.sub.ZS -m*a.sub.D).vertline.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: June 11, 1996
    Assignee: Daimler-Benz AG
    Inventors: Reinhard Zachai, Hans-Juergen Fuesser, Tim Gutheit
  • Patent number: 5523261
    Abstract: An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: June 4, 1996
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 5523256
    Abstract: A semiconductor laser according to the present invention includes: a semiconductor substrate; a multilayer structure provided on the semiconductor substrate, the multilayer structure including an active layer, a pair of cladding layers interposing the active layer, and current confining portion for injecting a current into a stripe-shaped predetermined region of the active layer, wherein the current confining portion includes a first current confining layer formed in regions excluding a region corresponding to the predetermined region of the active layer, the first current confining layer having an energy band gap larger than an energy band gap of the active layer and having a refractive index smaller than a refractive index of the active layer.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: June 4, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideto Adachi, Isao Kidoguchi, Kiyoshi Ohnaka, Satoshi Kamiyama
  • Patent number: 5522934
    Abstract: A plasma processing apparatus comprises a susceptor for supporting a target object to be processed having a target surface to be processed in a process vessel, a plurality of process gas supply nozzles for supplying a process gas for the target object into the process vessel, and an RF coil for generating an electromagnetic wave in the process vessel to generate a plasma of the process gas. The supplying nozzles have process gas injection holes formed at a plurality of levels in a direction substantially perpendicular to the target surface of the target object in the process vessel, and the gas injection holes located at an upper level are closer to a center of the target surface than gas injection holes located at a lower level.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: June 4, 1996
    Assignee: Tokyo Electron Limited
    Inventors: Akira Suzuki, Shuichi Ishizuka, Kohei Kawamura, Jiro Hata
  • Patent number: 5521120
    Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: May 28, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Jaim Nulman, Kenny K.-T. Ngan
  • Patent number: 5518955
    Abstract: A method of fabricating a quantum wire structure includes forming a first insulating film on a surface of a substrate of a first semiconductor, the insulating film including a pattern of spaced apart mask elements having a width not exceeding 100 nm; selectively growing a layer of a second semiconductor on the surface of the substrate employing the insulating film as a growth mask, the layer including spaced apart second semiconductor elements, each second semiconductor element having a trapezoidal cross-section transverse to the surface of the substrate and including an upper surface generally parallel to the surface of the substrate and sloped surfaces oriented so that a third semiconductor does not grow on the sloped surfaces; growing a layer of a third semiconductor having a smaller band gap energy than the band gap energies of the first and second semiconductors on the upper surfaces of the second semiconductor elements and on the surface of the substrate between adjacent second semiconductor elements bu
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: May 21, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiko Goto, Yutaka Mihashi
  • Patent number: 5518934
    Abstract: A multiwavelength local plane array infrared detector is included on a common substrate having formed on its top face a plurality of In.sub.x Ga.sub.1-x As (x.ltoreq.0.53) absorption layers, between each pair of which a plurality of InAs.sub.y P.sub.1-y (y.ltoreq.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: May 21, 1996
    Assignee: Trustees of Princeton University
    Inventors: Stephen R. Forrest, Gregory H. Olsen, Dong-Su Kim, Michael J. Lange
  • Patent number: 5516367
    Abstract: Vacuum CVD chambers are disclosed which provide a more uniformly deposited thin film on a substrate. The chamber susceptor mount for the substrate is heated resistively with a single coil firmly contacting the metal of the susceptor on all sides, providing uniform temperatures across the susceptor mount for a substrate. A purge gas line is connected to openings in the susceptor outside of the periphery of the substrate to prevent edge and backside contamination of the substrate. A vacuum feed line mounts the substrate to the susceptor plate during processing. A refractory purge guide, or a plurality of placement pins, maintain a fixed gap passage for the purge gases to pass alongside the edge of the wafer and into the processing area of the chamber. An exhaust pumping plate improves the uniformity of exhaustion of spent gases from the chamber.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: May 14, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Lawrence C. Lei, Ilya Perlov, Karl A. Littau, Alan F. Morrison, Mei Chang, Ashok K. Sinha
  • Patent number: 5516722
    Abstract: The present invention comprises a method and apparatus for increasing doping uniformity in semiconductor devices produced in a flow flange reactor. One aspect of the present invention involves dividing the flow flange (12) of the reactor into a plurality of sections (14, 16, 18). Each section (14, 16, 18) is then subdivided into a plurality of subsections (52, 54, 56) including a first subsection (52), a second subsection (54) and a third subsection (56). A group III gas may then be dispersed in the first subsection (52) of at least one section (18). A group V gas may then be dispersed in a second subsection (54) of that section, while a dopant gas may also be dispersed in a third subsection (56) of that section (18).
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: May 14, 1996
    Assignee: Texas Instruments Inc.
    Inventor: Tae S. Kim
  • Patent number: 5512510
    Abstract: A method for stably manufacturing, with improved reproducibility, a good amorphous silicon electrophotographic photosensitive member improved in potential characteristics such as chargeability and photoresponse as well as in the effect of reducing photo-memory and defects which cause spot image defects. A film is formed by plasma CVD on a base of the photosensitive member by using electromagnetic waves having a frequency of 13.56 MHz or higher as power for forming plasma under conditions that the spatial potential of plasma generated by the electromagnetic waves with respect to a base of the photosensitive member is not higher than 120 V and the current density of ions incident upon the base is not lower than 0.4 mA/cm.sup.2.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: April 30, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hitoshi Murayama, Satoshi Kojima
  • Patent number: 5507874
    Abstract: The present invention provides a method for removing particulate contaminants from an electrostatic chuck pedestal for a semiconductor workpiece by physical removal employing a soft material workpiece or by creating a plasma sheath which suspends the contaminants from the chuck surface and entrains them in the gas stream of the chamber vacuum exhaust system of the chamber. The contaminant removal processes are particularly effective in continuous plasma processes for the treatment of workpieces.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: April 16, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Yuh-Jia Su, Richard Muh
  • Patent number: 5500388
    Abstract: In order to form a film on a surface of a semiconductor wafer, a multiplicity of wafers are individually mounted on ring-shaped mounts of a wafer boat, while the temperature within a reaction tube is set at, e.g., 400.degree. C. under a nitrogen gas atmosphere. After loading the wafer boat into the reaction tube, the temperature within the reaction tube is raised up to, e.g., 620.degree. C. at a rate of, e.g., 100.degree. C./min, and SiH.sub.4 gas is supplied onto the surface of a silicon substrate to form a polysilicon film. After film formation, air is forced to flow along the internal surface of the heating section to forcibly cool the interior of the reaction tube. In the case of forming a metal silicon film using a wafer having a silicon substrate and a metal film formed on the surface of the silicon substrate, the temperature within the reaction tube is set at, e.g. 100.degree. C. for loading the wafers.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: March 19, 1996
    Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Tohoku Kabushiki Kaisha
    Inventors: Reiji Niino, Tomoyuki Ohbu, Hiroaki Ikegawa, Ken Nakao, Yoshiyuki Fujita, Tsutomu Haraoka, Makoto Kobayashi, Naoya Kaneda, Hiroshi Kumada
  • Patent number: 5500390
    Abstract: A method for controlling the Si concentration in a GaP single crystal layer grown in a series of runs of GaP liquid phase epitaxial growth with the repeated use of one and the same Ga solution, which comprise the steps of: measuring the Si concentrations of the GaP single crystal layers in preceding runs; then determining the additional Si amounts to be added into the Ga solution to refresh the Si effective concentration therein in reference to the Si concentrations in the layers; and adding Si of the thus determined amount into the Ga solution to commence the subsequent run, wherein the Si concentration in each of the GaP liquid phase epitaxial growth layers is determined from measurement of the O/G ratio in the layer, which is computed from each pair of the both values of the photoluminescent spectral peak intensity around the wavelength of 6300 .ANG. (O component) as the numerator and the other photoluminescent spectral peak intensity around the wavelength of 5540 .ANG.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 19, 1996
    Assignee: Shin-Etsu Handatoi Co., Ltd.
    Inventors: Munehisa Yanagisawa, Yuki Tamura, Norihide Kokubu
  • Patent number: 5499599
    Abstract: A method for growing a deposit upon a substrate of semiconductor material involves the utilization of pulsed laser deposition techniques within a low-pressure gas environment. The substrate and a target of a first material are positioned within a deposition chamber and a low-pressure gas atmosphere is developed within the chamber. The substrate is then heated, and the target is irradiated, so that atoms of the target material are ablated from the remainder of the target, while atoms of the gas simultaneously are adsorbed on the substrate/film surface. The ablated atoms build up upon the substrate, together with the adsorbed gas atoms to form the thin-film deposit on the substrate. By controlling the pressure of the gas of the chamber atmosphere, the composition of the formed deposit can be controlled, and films of continuously variable composition or doping can be grown from a single target of fixed composition.
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: March 19, 1996
    Assignee: Martin Marietta Energy Systems, Inc.
    Inventors: Douglas H. Lowndes, James W. McCamy
  • Patent number: 5498568
    Abstract: After a GaAs substrate is set in a reaction container, the pressure in the reaction container is reduced to 10-100 torr and arsine is supplied into the container. A GaAs buffer layer is formed on the GaAs substrate by introducing TMG when the surface temperature of the GaAs substrate is at 650.degree. C. Then, by stopping supply of TMG, the growth of the GaAs buffer layer is stopped (step I). Arsine is switched to phosphine. A time t after the switching, TMA, TMG and TMI adjusted at a predetermined mixing ratio beforehand are introduced into the container, thereby starting the formation of an InGaAlP layer on the GaAs buffer layer. During the growing process, the surface temperature of the GaAs substrate is raised to 750.degree. C. (step II). The InGaAlP layer is grown to a predetermined thickness with the surface temperature of the GaAs substrate being kept at 750.degree. C. (step III).
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 12, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Hosoba, Junichi Nakamura, Masanori Watanabe
  • Patent number: 5496767
    Abstract: A semiconductor laser comprises an optical wave guide layer including an AlGaInP active layer and AlGaInP optical confinement layers holding the active layer therebetween. A well structure of an energy band is formed and a compressive stress is applied to the activation layer by the difference between the compositions of the activation layer and the optical confinement layers. Since the compressive stress is applied to the activation layer, the oscillation threshold is lower than that of an un-strained device. Accordingly, the rise of the oscillation threshold due to the addition of Al is compensated and continuous oscillation at room temperature is attained and visible light having a wavelength of 0.67 .mu.m or lower, which has been difficult to attain in the past, is produce.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: March 5, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Ichiro Yoshida
  • Patent number: 5494850
    Abstract: This invention discloses a method to improve significantly the optical properties of rare-earth doped MBE-grown CaF.sub.2 films by annealing such films in a reducing atmosphere (e.g. forming gas) at appropriate temperatures (generally greater than 600 C. Films grown at the same temperature as that used later in the novel annealing process do not exhibit the same PL spectrum nor the high photoluminescence intensity emissions as annealed films. The intensity of the strongest peak 12a in FIG. 2 has a magnitude 3.6 times the intensity than the strongest peak 12 in as-grown film in FIG. 1. Similarly these same films annealed in an oxygen environment do not exhibit the have the desired properties.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: February 27, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Chen Cho, Walter M. Duncan
  • Patent number: 5491114
    Abstract: A continuous semiconductor thin film is formed by providing a sheet of a substrate material and applying a continuous layer of nanocrystals of the semiconductor material onto the substrate. The layer of nanocrystals is melted at a temperature below that of the bulk, but which is nonetheless adequate to melt the nanocrystals and cause them to fuse into a continuous thin film which forms a solid upon cooling. The nanocrystals may be sprayed onto the substrate, either from the liquid or gas phase. The substrate sheet is preferably tensioned during the application of the nanocrystalline layer, for example, with a set of rollers is used to provide the tensioning at a predetermined feed rate.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: February 13, 1996
    Assignee: Starfire Electronic Development & Marketing, Ltd.
    Inventor: Avery N. Goldstein