Patents Examined by Ramon A Mercado
  • Patent number: 11704240
    Abstract: A garbage data scrubbing method includes obtaining an input/output (IO) busy/idle status of a terminal at a current moment, where the IO busy/idle status includes a busy state and an idle state. When the IO busy/idle status of the terminal at the current moment is the idle state, a discard message is delivered to a storage device, where the discard message includes an initial address and a size of to-be-scrubbed physical space in the storage device, and where the discard message is used to unbind a mapping relationship between a physical address of the to-be-scrubbed physical space and a corresponding logical address.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 18, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Yu, Hao Chen, Bifeng Tong, Chengliang Zheng, Xiyu Zhou
  • Patent number: 11693772
    Abstract: A system and a method are disclosed that efficiently supports an append operation in an object storage system. A size of data received with a request for an append operation from an application is determined based on a data-alignment characteristic of a storage medium. Data that is not aligned with the data-alignment characteristic is stored in persistent memory and aggregated with other data from the application that is not aligned with the data-alignment characteristic, while data that is aligned with the data-alignment characteristic is stored directly in the storage medium. Aggregated data that becomes aligned with the data-alignment characteristic as additional requests for append operations are received are migrated to the storage medium.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 4, 2023
    Inventors: Angel Benedicto Aviles, Jr., Vinod Kumar Daga, Vamsikrishna Sadhu, Venkata Bhanu Prakash Gollapudi, Vijaya Kumar Jakkula
  • Patent number: 11693589
    Abstract: A storage device capable of maintaining consistency of data for the same address may include a memory device including a plurality of memory blocks, a buffer memory device including a plurality of cache buffers temporarily storing data previously received from a host, and a memory controller configured to receive a write request and a write data from the host and configured to control the buffer memory device and the memory device to store a previously received data, stored in one of the plurality of cache buffers with a logical address that matches a logical address of the write data, in the memory device before the write request is processed.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: July 4, 2023
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11662909
    Abstract: A system and method for efficiently maintaining metadata stored among a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores at least pairs of a key value and a physical pointer value. The levels are sorted by time. New records are inserted in a created new highest (youngest) level. No edits are performed in-place. A data storage controller determines both a cost of searching a given table exceeds a threshold and an amount of memory used to flatten levels exceeds a threshold. In response, the controller incrementally flattens selected levels within the table based on key ranges. After flattening the records in the selected levels within the key range, the records may be removed from the selected levels. The process repeats with another different key range.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: May 30, 2023
    Assignee: PURE STORAGE, INC
    Inventors: Marco Sanvido, Richard Hankins, Mark McAuliffe, Neil Vachharajani
  • Patent number: 11656797
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A plurality of access commands including a plurality of write commands are stored in a command queue, and the access commands are sorted into an execution order. A first write command is selected from the command queue based on the execution order, and a first part of the first write command is executed leaving a runt write command. The runt write command is executed between two of the sorted access commands so that the runt write command does not affect the execution order.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: David R. Hall
  • Patent number: 11650744
    Abstract: An electronic device may implement a virtual elastic queue in memory, where, as needed, the virtual elastic queue grows in size to accommodate more queue elements, or shrinks in size to free up queue-element capacity and space in the memory. The virtual elastic queue may include a virtual queue and one or more physical queues, where the virtual queue provides a mapping to the one or more physical queues, and where a data structure may represent queue elements in the one or more physical queues. Notably, the virtual queue may point to the one or more physical queues, and the one or more physical queues may point to physical queue memory where data elements are enqueued and dequeued. Note that the virtual elastic queue may not have a predefined memory size and, up to a size of the memory, may not be constrained.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 16, 2023
    Assignee: ARRIS Enterprises LLC
    Inventor: Rakesh G. Hansalia
  • Patent number: 11630605
    Abstract: A memory system comprises a plurality of memory sub-systems, each with a memory bank and other circuit components. For each of the memory sub-systems, a first buffer receives and stores a read-modify-write request (with a read address, a write address and a first operand), a second operand is read from the memory bank at the location specified by the read address, a combiner circuit combines the first operand with the second operand, an activation circuit transforms the output of the combiner circuit, and the output of the activation circuit is stored in the memory bank at the location specified by the write address. The first operand and the write address may be stored in a second buffer while the second operand is read from the memory bank. Further, the output of the activation circuit may be first stored in the first buffer before being stored in the memory bank.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 18, 2023
    Assignee: Recogni Inc.
    Inventors: Gary S. Goldman, Ashwin Radhakrishnan
  • Patent number: 11625194
    Abstract: The present disclosure includes apparatuses and methods updating a register in memory. An example includes an array of memory cells; and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated to access the data stored in the array of memory cells.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Isom Crawford, Jr.
  • Patent number: 11625181
    Abstract: Data tiering based on snapshots, including: receiving information describing, for data stored in a storage system, any snapshots associated with the data and any volumes storing the data; determining, from a plurality of storage tiers, a storage tier for the data based on the information; and storing the data in a storage device of the storage system associated with the storage tier.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: April 11, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Andrew Bernat, Zoltan Dewitt, John Colgrove
  • Patent number: 11626735
    Abstract: A method, apparatus, system and computer program is provided for optimizing and controlling volt-amperes reactive on an electrical control system. System-level and local-level measurements are determined and analyzed to prioritize and optimize which VAR adjusters are adjusted.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 11, 2023
    Assignee: Dominion Energy, Inc.
    Inventors: Stephen J. Tyler, Melissa A. Peskin
  • Patent number: 11625195
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 11, 2023
    Assignee: SK hynix Inc.
    Inventors: In Ho Jung, Ji Woon Yang, Gi Jo Jeong, Seung Duk Cho
  • Patent number: 11620258
    Abstract: An information processing apparatus includes an acquiring part, a copying part, and a switching part. The acquiring part acquires a file structure at a migration source and one or more identification information items each of which identifies a file at the migration source. The copying part copies the file structure and the one or more identification information items to a migration destination before migration of content data of one or more files at the migration source. In response to detection of an operation on a file corresponding to one of the one or more identification information items copied to the migration destination by the copying part, the switching part switches an access destination to the file at the migration source if a migration time to complete migration of content data of the file and finish the operation is equal to a predetermined duration or more.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: April 4, 2023
    Assignee: FUJIFILM Business Innovation Corp.
    Inventor: Yusuke Shirai
  • Patent number: 11614889
    Abstract: An operation combiner receives a series of commands with read addresses, a modification operation, and write addresses. In some cases, the commands have serial dependencies that limit the rate at which they can be processed. The operation combiner compares the addresses for compatibility, transforms the operations to break serial dependencies, and combines multiple source commands into a smaller number of aggregate commands that can be executed much faster than the source commands. Some embodiments of the operation combiner receive a first command including one or more first read addresses and a first write address. The operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 28, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christopher J. Brennan
  • Patent number: 11616773
    Abstract: Some embodiments of the invention provide systems and methods for securing configuration information for cloud-based services. Some embodiments include a system comprising a data store and data sets including plant process information and configuration information. A memory device stores computer-executable instructions executable by a processor coupled to the cloud service. When executed, the instructions receive configuration information, store it in a data file, apply a generated certificate to the file, and deploy the resulting protected configuration data file to the cloud-based service. In addition, the protected configuration data file is made available by obtaining the file from the cloud-based service.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: March 28, 2023
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Ryan Benedict Saldanha, Vinay T. Kamath, Peijen Lin, Abhijit Manushree
  • Patent number: 11580026
    Abstract: In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The first control unit may be configured to obtain, from the second control unit, a first memory address associated with a data reading process of the second processing unit, receive a write request from the first processing unit, the read request having an associated second memory address, and write data into the memory region based on the write request in response to a determination that the second memory address falls outside of the guarded reading region.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 14, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Vlad Fruchter, Richard Lawrence Greene, Hideo Tamama
  • Patent number: 11561725
    Abstract: Embodiments of the present disclosure relate to a system and an operating method thereof. According to embodiments of the present disclosure, a memory system may transmit a first type response indicating that first data has been cached in a cache to the host when receiving a first command requesting to write the first data from the host, and may transmit a second type response indicating success or failure of an operation of storing the first data in the memory device to the host after transmitting the first type response to the host. Further, the host may delete the first data from a write buffer after the operation of storing the first data in the memory device succeeds.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Hye Mi Kang, Eu Joon Byun
  • Patent number: 11556428
    Abstract: Provided is a backup system including a storage system and a backup server, in which the backup server includes a ledger for managing a copy number and a backup acquisition date and time for each backup image, a data volume that stores data accessed by a business server, a backup image volume that stores a plurality of backup images at different time points of the data volume, an access volume having a volume ID for accessing the backup image from the backup server, and a data protection area including at least one volume having an internal volume ID instead of the volume ID for accessing from the backup server are configured in the storage system, and the backup image stored in the data protection area and the access volume are associated, and the backup image in the data protection area is provided to the backup server.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: January 17, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tanaka, Goro Kazama, Naoyuki Masuda, Tomoya Yamada, Yuri Hiraiwa
  • Patent number: 11544187
    Abstract: A distributed storage system node is disclosed. The distributed storage system node may include at least one storage device, which may act as the primary replica for data subject to an Input/Output (I/O) request. A cost analyzer may calculate a local estimated time required to complete the I/O request at the primary replica, and a remote estimated time required to complete the I/O request at a secondary replica of the data. An I/O redirector may direct the I/O request to either the primary replica or the secondary replica based on the local estimated time required and the one remote estimated time required.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 3, 2023
    Inventors: Vikas K. Sinha, Gunneswara Rao Marripudi, Jianjian Huo, Ajit Yagaty
  • Patent number: 11533304
    Abstract: Systems and methods for securing configuration information for cloud-based services. A system comprises a data store and data sets including plant process information and configuration information. A memory device stores computer-executable instructions. When executed by a processor coupled to the cloud service, the instructions receive configuration information, store it in a data file, apply a generated certificate to the file, and deploy the resulting protected configuration data file to the cloud-based service. In addition, the protected configuration data file is made available by obtaining the file from the cloud-based service.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: December 20, 2022
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Ryan B. Saldanha, Vinay T. Kamath, Peijen Lin, Abhijit Manushree
  • Patent number: 11531496
    Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: December 20, 2022
    Inventors: Yongsuk Kwon, Jinin So, Jonggeon Lee, Kyungsoo Kim, Jin Jung, Jeonghyeon Cho