Abstract: A method and apparatus for data exchange between a master microprocessor and a slave microprocessor, in which the connection is a parallel bus and the data exchange requires a minimum of time. For this purpose, the data are transmitted in a predetermined sequence and in which the transmission-start identifier is a signal train generated by the master processor which is specifically associated with data transmission. Preferably, a master processor and a slave processor are interconnected by the parallel data bus, with buffer memories, such as latches, interposed. A toggle flip-flop is connected to the interrupt input of the slave processor in such a way that merely placing a specific instruction (i.e. command+data) on the bus simultaneously notifies the slave processor to prepare for the exchange of data, thereby saving time.

Abstract: A Direct Memory Access Controller includes first and second registers respectively to which first and the second offset data are supplied, as well as a register to which source address data is supplied and a register to which destination address data is supplied. Every time one data item is transferred from one memory to the other, the source address data and the destination address data are updated respectively by values designated by the first offset data and the second offset data. Address data can be updated both increasingly and decreasingly. According to the Direcet Memory Access Controller of this construction, the transfer of data such as a rotational operation of graphic data stored within the image memory can be achieved without increasing the burden imposed upon the microprocessor.

Abstract: A method of modifying a graphics data stream for improving printer throughput. The data stream is scanned and nulls preceding printable data are converted to text spaces. Text spaces are recognized by the printer to cause a printhead included in the printer to move directly to the first printable data position rather than homing first.

Abstract: An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

Abstract: A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.

Abstract: A data bus discharging circuit capable of enabling the high-speed operation of a microprocessor, includes a control signal generating circuit which provides control signals, a precharge/enable signal generating circuit which provides a precharge control signal and an enable signal, a discharge detecting circuit which detects small changes in the potential of the bit lines of the data bus, and a discharging circuit which sets the bit lines of the data bus selectively at a ground potential in response to the discharge detecting circuit.

Abstract: A systolic array (1) for reducing the time required to solve an algorithm having cyclic loop dependency, i.e., nested loops in which values calculated by inner loops depend upon indices of said inner loops and upon indices of outer loops. The array (1) comprises a chain of several identical serially connected and sequentially accessed cells. In the preferred embodiment, each cell, except for first and last cells in the chain, is connected to its two adjacent cells only. Multiprocessing is employed: at certain times during the algorithm solving, more than one cell is simultaneously activated to perform portions of the solving, so that the total time required to solve the algorithms is shortened to be a linear function of n.times.m. The algorithm can represent measurement of the distance between two symbolic strings, or other problems in artificial intelligence or logic.

Abstract: A memory card has a card medium and a laser memory for storing data. A data processing section for storing encryption and/or decryption key data, an encryption and/or decryption program and a password is arranged in the card medium. When the same password as prestored in the data processing section is input, the input data is encrypted and/or decrypted in accordance with the encryption and/or decryption key data and the encryption and/or decryption program. The encrypted and/or decrypted data is stored in the laser memory.

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.