Patents Examined by Ratisha Mehta
-
Patent number: 11967647Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.Type: GrantFiled: June 28, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Blandine Duriez, Marcus Johannes Henricus Van Dal, Martin Christopher Holland, Gerben Doornbos, Georgios Vellianitis
-
Patent number: 11961872Abstract: A unit pixel includes a transparent substrate, a plurality of light emitting devices disposed on the transparent substrate, and an electrostatic discharge (ESD) protector disposed on the transparent substrate and protecting at least one of the light emitting devices from electrostatic discharge.Type: GrantFiled: April 28, 2021Date of Patent: April 16, 2024Assignee: SEOUL VIOSYS CO., LTD.Inventors: Namgoo Cha, Sang Min Kim, Jae Hee Lim
-
Patent number: 11961938Abstract: A method of processing light-emitting elements includes: transferring a plurality of light-emitting elements from original wafers or next-stage carriers, based on a predetermined pattern. The predetermined pattern arranges two adjacent LED groups in a first direction on the original wafer or carriers to be placed on two non-adjacent positions in the first direction on the next-stage carriers. The light-emitting elements on the original wafer have a horizontal wafer pitch and a vertical wafer pitch. The light-emitting elements on each of the next-stage carriers have a first horizontal pitch and a first vertical pitch. The first horizontal pitch is greater than the horizontal wafer pitch, or the first vertical pitch is greater than the vertical wafer pitch. Besides, a light-emitting element device using the aforementioned method is also provided.Type: GrantFiled: March 13, 2020Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Min-Hsun Hsieh, Chang-Lin Lee
-
Patent number: 11955587Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.Type: GrantFiled: April 12, 2021Date of Patent: April 9, 2024Assignee: Unimicron Technology Corp.Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
-
Patent number: 11948815Abstract: Mass transfer tools and methods for high density transfer of arrays of micro devices are described. In an embodiment, a mass transfer tool includes a micro pick up array with an array of transfer heads arranged in clusters. The clusters of transfer heads can be used to pick up a high density group of micro devices followed by sequential placement onto a receiving substrate.Type: GrantFiled: June 11, 2021Date of Patent: April 2, 2024Assignee: Apple Inc.Inventors: Antoine Manens, Dariusz Golda, Hyeun-Su Kim
-
Patent number: 11942589Abstract: Disclosed herein is an LED device that includes a display package and a plurality of LED dies arranged on a top surface of the display package. The display package includes a molding compound, a backplane die, and at least one spacer structure, with the backplane die and the at least one spacer structure being embedded within the molding compound. In some embodiments, the plurality of LED dies includes a first die containing red LEDs, a second die containing green LEDs, and a third die containing blue LEDs. The backplane die includes driver circuits configured to drive LEDs in the plurality of LED dies, for example, LEDs of the first die, the second die, and the third die. The at least one spacer structure has a higher thermal conductivity than the molding compound and is configured to dissipate heat generated by the LEDs in the plurality of LED dies.Type: GrantFiled: May 12, 2022Date of Patent: March 26, 2024Assignee: META PLATFORMS TECHNOLOGIES, LLCInventor: Rajendra D. Pendse
-
Patent number: 11942568Abstract: A light-emitting diode device includes an epitaxial structure that contains first-type and second-type semiconductor units and an active layer interposed therebetween, a light transmittable dielectric element that is disposed on the first-type semiconductor unit opposite to the active layer and is formed with a first through hole, an adhesive layer that is disposed on the dielectric element and is formed with a second through hole corresponding in position to the first through hole, and a metal contact element that is disposed on the adhesive layer. The adhesive layer has a thickness of at most one fifth of that of the dielectric element. The metal contact element extends into the first and second through holes, and electrically contacts the first-type semiconductor unit. A method for manufacturing the LED device is also disclosed.Type: GrantFiled: June 15, 2020Date of Patent: March 26, 2024Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.Inventors: Dongyan Zhang, Yuehua Jia, Cheng Meng, Jing Wang, Chun-I Wu, Duxiang Wang
-
Patent number: 11935987Abstract: A light emitting diode (LED) array comprises non-segmented pixels in a light-emitting pixel area providing optical efficiency and minimizing dark-grid appearance. The LED array comprises: a monolithic body, a light-emitting pixel area, a plurality of anodes, a common cathode, and one or more dielectric materials. The light-emitting pixel area is integral to the monolithic body. The light-emitting pixel area includes semiconductor layers comprising: a second portion of an N-type layer, an active region, and a P-type layer. The monolithic body comprises a first portion of an N-type layer, and the second portion of the N-type layer is integral to the first portion of the N-type layer. Each anode comprises a P-contact layer and one or more P-contact materials, each P-contact layer is in contact with the P-type layer. The common cathode comprises one or more N-contact materials in contact with the first portion of the N-type layer.Type: GrantFiled: October 25, 2022Date of Patent: March 19, 2024Assignee: Lumileds LLCInventors: Toni Lopez, Erik William Young, Rajiv Pathak
-
Patent number: 11923491Abstract: An electronic device, including a substrate, an edge wire, a first protection layer, and a second protection layer, is provided. The substrate has a first surface, a second surface, and a side surface connecting the first surface and the second surface. A normal vector of the side surface is different from the first surface and the second surface. The edge wire is configured on the substrate, extending from the first surface to the second surface while passing through the side surface. The first protection layer is configured on the edge wire. The edge wire is sandwiched between the substrate and the first protection layer. The edge wire and the first protection layer form an undercut structure. The second protection layer is configured on the substrate and fills the undercut structure. A manufacturing method of an electronic device is also provided.Type: GrantFiled: July 15, 2021Date of Patent: March 5, 2024Assignee: Au Optronics CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
-
Patent number: 11923372Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.Type: GrantFiled: May 5, 2021Date of Patent: March 5, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
-
Patent number: 11916129Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.Type: GrantFiled: June 15, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Chandra Mouli
-
Patent number: 11908985Abstract: A display device may include a display panel including a pad disposed on a substrate and a driving unit including a bump electrically connected to the pad. The pad may include a first layer disposed on the substrate and including a conductive material, a second layer disposed on the first layer and including patterns arranged in a first direction and spaced apart from each other, and a third layer disposed on the second layer and including a conductive material. The first layer may include portions protruding toward the substrate and respectively corresponding to the patterns.Type: GrantFiled: February 19, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Dae Geun Lee, Joon Sam Kim, Suk Ho Choi
-
Patent number: 11901479Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first microelectronic elements on a first temporary substrate; and replacing at least one defective microelectronic element of the first microelectronic elements with at least one second microelectronic element. The first microelectronic elements and at least one second microelectronic element are distributed on the first temporary substrate. The first microelectronic elements and at least one second microelectronic element have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first microelectronic elements and at least one second microelectronic element. A semiconductor structure and a display panel are also provided.Type: GrantFiled: May 19, 2021Date of Patent: February 13, 2024Assignee: PlayNitride Display Co., Ltd.Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
-
Patent number: 11894499Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and lens arrangements for packaged LED devices are disclosed. An LED package may include one or more LED chips on a submount with a lens positioned on the submount to form a cavity. The one or more LED chips may reside in the cavity without direct encapsulation materials that would otherwise contact the one or more LED chips and any corresponding wirebonds. In this manner, the one or more LED chips may be driven with higher drive currents while reducing degradation and mechanical strain effects related to differences in coefficients of thermal expansion with typical encapsulant materials. LED packages may also be configured with one or more apertures that allow air flow between an interior volume of a cavity and an ambient environment outside the LED package to promote heat dissipation at higher drive currents.Type: GrantFiled: July 1, 2020Date of Patent: February 6, 2024Assignee: CreeLED, Inc.Inventors: Robert Wilcox, Derek Miller, Kyle Damborsky, Aaron Francis, Colin Blakely
-
Patent number: 11894489Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor layer, an active region, a p-type or n-type layer, and a first metal element-containing structure. The first semiconductor layer has a surface including a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP or AlGaInP. The p-type or n-type layer includes an oxygen element (O) and a metal element, and is located on the second portion. The first metal element-containing structure is located on the p-type or n-type layer. The p-type or n-type layer physically contacts the first metal element-containing structure and the first semiconductor layer.Type: GrantFiled: March 16, 2021Date of Patent: February 6, 2024Assignee: EPISTAR CORPORATIONInventors: Min-Hsun Hsieh, Yu-Tsu Lee, Wei-Jen Hsueh
-
Patent number: 11888085Abstract: A method of transferring micro-light emitting diodes is provided. The method includes preparing a transfer substrate including a first groove, a second groove, and a third groove; forming a first transfer prevention film on the second groove and forming a second transfer prevention film on the third groove; transferring, into the first groove, a first micro-light emitting diode configured to emit a first color light; removing the first transfer prevention film formed on the second groove; transferring, into the second groove, a second micro-light emitting diode configured to emit a second color light; removing the second transfer prevention film formed on the third groove; and transferring, into the third groove, a third micro-light emitting diode configured to emit a third color light.Type: GrantFiled: March 8, 2023Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seogwoo Hong, Junsik Hwang, Hyunjoon Kim, Joonyong Park, Kyungwook Hwang
-
Patent number: 11882701Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.Type: GrantFiled: May 28, 2021Date of Patent: January 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventor: Seok Cheon Baek
-
Patent number: 11875994Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.Type: GrantFiled: January 7, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chih-Tsung Wu
-
Patent number: 11862751Abstract: A manufacturing method for an LED includes: providing a substrate having an upper surface divided into a plurality of zones; a LED group formed on each of the zones and wherein: a plurality of the LED groups includes a first LED group; and the LEDs of the first LED group include a defective LED; forming a testing circuit on the substrate to electrically connect the LEDs; testing the first LED group by the testing circuit; recording a position of the defective LED; providing a carrier; and performing one of the following steps by the position of the defective LED: removing the defective LED from the substrate and then transferring the other LEDs in the first LED group to the carrier; transferring the other LEDs other than the defective LED in the first LED group to the carrier; or transferring the LEDs to the carrier and repairing it on the carrier.Type: GrantFiled: February 5, 2021Date of Patent: January 2, 2024Assignee: EPISTAR CORPORATIONInventors: Chia-Chen Tsai, Jia-Liang Tu, Chi-Ling Lee
-
Patent number: 11862663Abstract: A display panel and a display device are provided. The display panel includes a first display area and a second display area corresponding to a position of an electronic component, wherein a light transmittance of the second display area is greater than a light transmittance of the first display area. A plurality of pixel units are disposed in the second display area, a ratio of a number of the first sub-pixels to the second sub-pixels and the third sub-pixels is 1:1:2 in each of the pixel units of the second display area, and by providing pixels with larger intervals in the second display area, a light transmittance above the electronic component is increased.Type: GrantFiled: May 26, 2020Date of Patent: January 2, 2024Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventors: Jiuhong Peng, Shiyan Xiao