Patents Examined by Ratisha Mehta
  • Patent number: 10381298
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 10369664
    Abstract: The yield of a manufacturing process of a semiconductor device is increased. The mass productivity of the semiconductor device is increased. The semiconductor device is manufactured by performing a step of performing plasma treatment on a first surface of a substrate; a step of forming a first layer over the first surface with the use of a material containing a resin or a resin precursor; a step of forming a resin layer by performing heat treatment on the first layer; and a step of separating the substrate and the resin layer from each other. In the plasma treatment, the first surface is exposed to an atmosphere containing one or more of hydrogen, oxygen, and water vapor.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Seiji Yasumoto, Naoto Goto, Satoru Idojiri
  • Patent number: 10373821
    Abstract: Disclosed is a substrate processing method including gas injection including a source material containing silicon towards substrates received in a reaction chamber, depositing the source material on the substrates by generating plasma including oxygen radicals so as to form deposition films, and executing surface treatment of the deposition films by injecting plasma gas including oxygen radicals.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 6, 2019
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Seung Chul Shin, Jin Hyuk Yoo, Min Ho Cheon, Chul-Joo Hwang
  • Patent number: 10361090
    Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Patrick Morrow, Donald Nelson
  • Patent number: 10361081
    Abstract: Processes and systems for carbon ion implantation include utilizing phosphine as a co-gas with a carbon oxide gas in an ion source chamber. In one or more embodiments, carbon implantation with the phosphine co-gas is in combination with the lanthanated tungsten alloy ion source components, which advantageously results in minimal oxidation of the cathode and cathode shield, among other components within the ion source chamber.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 23, 2019
    Assignee: AXCELIS TECHNOLOGIES, INC.
    Inventors: Neil Colvin, Tseh-Jen Hsieh
  • Patent number: 10359788
    Abstract: A decoder for a two-wire irrigation system is disclosed, having the ability to be remotely updated with new firmware over the two-wire network, the ability to download irrigation commands that can be executed at a later time, the ability to adjust its data speed when data corruption is encountered, and the ability to sense the position of an attached solenoid plunger.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 23, 2019
    Assignee: The Toro Company
    Inventors: Adrian Gutierrez, Alex Korol
  • Patent number: 10355177
    Abstract: To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 16, 2019
    Assignee: CITIZEN ELECTRONICS CO., LTD.
    Inventor: Hideyoshi Horie
  • Patent number: 10355231
    Abstract: An organic light emitting display device comprises two emission portions between first and second electrodes, wherein at least one among the two emission portions includes two emitting layers, whereby efficiency and a color reproduction ratio may be improved.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sung Hoon Pieh, Chang Wook Han, Hong Seok Choi, Ki-Woog Song, So Yeon Ahn, Seung Hyun Kim
  • Patent number: 10347509
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes molding and curing a framing member having an upper side that defines an array of indentations. Semiconductor dies are then adhered to the framing member within respective indentations. The upper side of the framing member and the dies are covered with an RDL. Formation of the RDL includes deposition of a dielectric material that also fills gaps between the dies and the framing member within the indentations. The framing member can be molded to have a thickness that can provide mechanical strength to resist damage to the dies during the formation of the RDL or other manufacturing processes, for example due to warping of the dies. After the RDL is completed, this excess framing member material can then be removed from lower side of the framing member and the structure can be diced to separate the dies into respective semiconductor devices.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 9, 2019
    Assignee: DIDREW TECHNOLOGY (BVI) LIMITED
    Inventor: Minghao Shen
  • Patent number: 10340368
    Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz, Yunpeng Yin
  • Patent number: 10332957
    Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna
  • Patent number: 10325785
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 10319776
    Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: June 11, 2019
    Assignee: TRUSTEES OF DARTMOUTH COLLEGE
    Inventors: Jiaju Ma, Eric R. Fossum
  • Patent number: 10319629
    Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein a portion of the intervening metallization level (MX+1) is in a pathway of the skip via.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Brent A. Anderson, Nicholas A. Lanzillo
  • Patent number: 10312277
    Abstract: A variable optical filter is disclosed including a bandpass filter and a blocking filter. The bandpass filter includes a stack of alternating first and second layers, and the blocking filter includes a stack of alternating third and fourth layers. The first, second and fourth materials each comprise different materials, so that a refractive index of the first material is smaller than a refractive index of the second material, which is smaller than a refractive index of the fourth material; while an absorption coefficient of the second material is smaller than an absorption coefficient of the fourth material. The materials can be selected to ensure high index contrast in the blocking filter and low optical losses in the bandpass filter. The first to fourth layers can be deposited directly on a photodetector array.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 4, 2019
    Assignee: VIAVI Solutions Inc.
    Inventors: Karen Denise Hendrix, Charles A. Hulse, Richard A. Bradley, Jeffrey James Kuna
  • Patent number: 10312367
    Abstract: High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Kinyip Phoa, Nidhi Nidhi, Chia-Hong Jan, Ting Chang
  • Patent number: 10312217
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 4, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 10312249
    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Chuan Sun, Wei Ta, Wang Xiang
  • Patent number: 10304746
    Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
  • Patent number: 10304878
    Abstract: An image sensor is provided which is capable of holding data for one frame period or longer and conducting a difference operation with a small number of elements. A photosensor is provided in each of a plurality of pixels arranged in a matrix, each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for the data holding portion, a transistor with small leakage current (sufficiently smaller than 1×10?14 A) is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda