Abstract: In an embodiment, an example computer-implemented method for configuring a hardware accelerator to perform a non-linear function involves: determining a plurality of intervals that partition an input domain of the non-linear function; determining a plurality of subinterval configurations corresponding to different numbers of subintervals for partitioning that interval; generating an error set comprising an error for using a polynomial function to approximate the non-linear function within one or more corresponding subintervals specified by the subinterval configuration; using the error set and resource constraints, selecting one of the subinterval configurations for each of the intervals to generate a configuration set that minimizes a worst-case error across the intervals; selecting one of the subinterval configurations for each of the intervals to generate an improved configuration set that minimizes a cumulative error across the intervals without exceeding the worst-case error; and configuring the hardware

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: Systems and techniques for automated transfer of peripheral device operations are described herein. In an example, a system may adapted so that, while a first device of a first type and a second device of the first type are simultaneously connected to a client device, the first device, rather than the second device, is used as an active device of the first type for at least one application, the first and second devices being peripheral devices. The system may be further adapted so that, while both the first and second devices remain connected to the client device, a switch from the first device to the second device by a user is determined, and, based on the switch from the first device to the second device, the second device, rather than the first device, is used as the active device of the first type for the at least one application.

Abstract: An adapting device according to an embodiment includes: a first storage unit configured to store correspondence information representing a correspondence relation between processing requested by a higher-level system and a method for implementing the processing in a lower-level system; a conversion unit configured to convert a processing request from the higher-level system to the lower-level system into a processing procedure capable of being implemented in the lower-level system and supply the processing procedure to the lower-level system; and an additional information processing unit configured to generate additional information to be supplied to the lower-level system together with the processing procedure.

Abstract: An all-in-one computer includes a display, a Universal Serial Bus (USB) Type-C port, a plurality of USB Type-A ports, a USB hub, a demultiplexer, and a Power Delivery (PD) controller. The USB hub is coupled to the plurality of USB Type-A ports. The demultiplexer is coupled between the display, the USB Type-C port, and the USB hub. The PD controller is to control the demultiplexer and the USB hub to pass a display signal input to the USB Type-C port to the display and pass signals input to the USB hub from the plurality of USB Type-A ports to the USB Type-C port with a computing device coupled to the USB Type-C port.

Abstract: A portable electronic device includes a main system circuit, a storage, a power button, a power-off trigger circuit, a system power-off circuit, a power supply circuit, and a configuration power-off circuit. The power-off trigger circuit is coupled to the power button and provides a system power-off signal and a configuration power-off signal when the power button is detected to be continuously pressed and a pressing time is greater than a predetermined time. The system power-off circuit is coupled to the power-off trigger circuit and the power supply circuit and stops providing the main system circuit with a system power supply voltage provided by the power supply voltage according to the system power-off signal. The configuration power-off circuit is coupled to the power-off trigger circuit and the storage and drives the configuration power supply voltage provided to the storage down to a ground voltage according to the configuration power-off signal.

Abstract: A bus arrangement includes a coordinator, a first subscriber having a first optical display, a second subscriber having a second optical display, a third subscriber having a third optical display, and a bus that couples the coordinator to the first, second, and third subscribers. In a standard operating phase, the first subscriber is configured to display first local information of the first subscriber on the first optical display, the second subscriber is configured to display second local information of the second subscriber on the second optical display, and the third subscriber is configured to display third local information of the third subscriber on the third optical display. The coordinator is configured to switch from a standard operating phase to a display operating phase based on detecting a fault in the first subscriber.

Abstract: Disclosed are a data transmission apparatus and method, used for transmitting data between a transmitter and a receiver connected by N data lines, N being an integer greater than 1. The method comprises: sending a plurality of data units one by one; on each transmission signal, inverting the level of one and only one data line corresponding to the currently sent data unit; extracting the transmission signal, and decoding the data unit corresponding to the data line according to the data line of which level is inverted among the N data lines; and sampling the data unit and then outputting.

Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.

Abstract: One embodiment facilitates measurement of a performance of a storage device. During operation, the system determines a normalized cost for an I/O request, wherein the normalized cost is independent of an access pattern and a type of the I/O request, wherein the normalized cost is indicated by a first number of virtual I/O operations consumed by the I/O request, and wherein a virtual I/O operation is used as a logical unit of cost associated with physical I/O operations. The system identifies a performance metric for the storage device by calculating a second number of virtual I/O operations per second which can be executed by the storage device. The system allocates incoming I/O requests to the storage device based on the performance metric, e.g., to satisfy a Quality of Service requirement, thereby causing an enhanced measurement of the performance of the storage device.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Abstract: Removeable couplings are provided for connecting a memory module to a host processor of an IHS (Information Handling System). The coupling includes electrical contacts and fasteners for positioning the electrical contacts within an empty memory slot of the IHS motherboard. The housing extends between two ends of the coupling and receives the memory module when the memory module is installed in the IHS. The positioned electrical contacts are then seated within the memory slot of the motherboard by the downward force applied by an administrator in installing the memory module to the coupling. The force applied in installing the memory module also serves to connect the electrical contacts of the coupling to a memory channel of the motherboard. The removeable coupling is not attached to the motherboard when the memory module is not installed in the IHS, thus eliminating signal stubs in the memory channel.

Abstract: Provided is an extension module for independently storing calibration data, including: a first interface, adapted to receive a first external input signal; a second interface, adapted to output the first output signal of the extension module; a signal processing circuit, connected between the first interface and the second interface; and a first memory, the first memory storing first calibration data, and the first calibration data being associated with the extension module. Furthermore, also provided is a component using the above extension module, and a component calibration method. On the one hand, the extension module of an embodiment may share an ADC sampling circuit on a main module, so that the manufacturing cost of the extension module is reduced. On the other hand, an embodiment can facilitate the replacement of different extension modules for the main module without repeated calibration.

Abstract: Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

Abstract: Modular transaction terminal services are provided. The services are customized for specific features using configuration data maintained in files. The services communicate using a standardized data format and Application Programming Interface (API). An interface is provided for custom defining an instance of a processing environment for a target transaction terminal. Customizations are made to the files and process flow data structures that are processed by the services. The hardware requirements of the target transaction terminal are also obtained and an installation package is created for the target transaction terminal. The installation package is installed on hardware of the target transaction terminal and the processing environment initiated. The services, configuration data maintained in files, process flow data structures, and interface represent a modularized and customizable transaction terminal architecture.

Abstract: As described herein, a method performed in response to a client device undergoing an at least partial warm reset or reboot may include receiving a firmware commit request from a client device. The method may also include writing, at a first time, a firmware image associated with the client device into execution memory of volatile memory. The method may also include writing, at a second time, the firmware image associated with the client device into a memory slot of non-volatile memory.

Abstract: Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.

Abstract: A thread executing a task at a node in a multi-socket computing system may access a first data structure to obtain a first calibration dataset for the node. The first thread may generate a timestamp based on the first calibration dataset and a first quantity of time measured by a clock at the first node. The real-time duration of the task may be determined based on the timestamp. The first thread may recalibrate the first clock by at least generating, based on the first quantity of time measured by the clock and a second quantity of time measured by a wall clock of an operating system of the multi-socket computing system, a second calibration dataset. The first thread may update the first data structure to include the second calibration dataset while a second thread accesses a second data structure to obtain calibration data.

Abstract: The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.