Patents Examined by Raymond N Phan
  • Patent number: 10805398
    Abstract: A door controller with an integrated data collection and transmission device, which comprises a motor driving module, a bus communication module, a vehicle door opening/closing control module, a parameter control module, and a data collection and transmission device. The data collection and transmission device is configured to receive and process four types of data collected by a motor driving data collection unit, a vehicle door opening/closing control data collection unit, an operation parameter collection unit, and a bus communication data collection unit, and transmit the four types of processed data to a background server.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 13, 2020
    Assignee: NANJING KANGNI MECHANICAL & ELECTRICAL CO., LTD.
    Inventors: Zhixing Xu, Xiaopeng Hou, Aiqing Wang, Xiang Shi
  • Patent number: 10795687
    Abstract: An information processing system includes a first information processing device, and a second information processing device, wherein the first information processing device includes a first memory that stores first firmware in which first setting information related to a first setting of first hardware of the first information processing device is recorded, and a first processor configured to generate, by executing the first firmware, data including the first setting information recorded in the first firmware, and the second information processing device includes a second memory that stores second firmware for reproducing the first setting in setting processing of second hardware of the second information processing device based on the first setting information included in the generated data, and a second processor configured to reproduce, by executing the second firmware, the first setting based on the first setting information in the setting processing of the second hardware.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 6, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Takanori Okayasu
  • Patent number: 10795399
    Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf Kuehnis, Enrico Carrieri
  • Patent number: 10789195
    Abstract: A non-transitory computer-readable storage medium may be executable by a processor to receive a designation of a message bus producer, a set of business logic to be stored in a set of containers, a designation of a message bus consumer, and a designation of a set of message-handling functions. The non-transitory computer-readable storage medium may generate a serverless application stack, based upon the message bus producer, the set of business logic, the message bus consumer, and the set of message-handling functions. The non-transitory computer-readable storage medium may cause the serverless application stack to receive a message stream from the message bus producer as streaming data, process the message stream according to at least one function, stored in the set of containers, perform at least one message-handling function of the set of message-handling functions on the message stream, and transport the set of messages to the message bus consumer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: September 29, 2020
    Assignee: Capital One Services, LLC
    Inventor: Maharshi Jha
  • Patent number: 10782772
    Abstract: An energy-aware system, and method thereof are provided. The energy-aware system includes a microcontroller; an energy storage; a plurality of execution functions integrated in a system on chip (SoC); and a scheduler configured to schedule execution of operations based on available energy at the energy storage and energy requires to complete each of the operations.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 22, 2020
    Assignee: WILIOT, LTD.
    Inventors: Yaron Elboim, Dotan Ziv, Yuval Amran, Nir Shapira
  • Patent number: 10783075
    Abstract: The disclosed technology is generally directed to data security. In one example of the technology, data is stored in a memory. The memory includes a plurality of memory banks including a first memory bank and a second memory bank. At least a portion of the data is interleaved amongst at least two of the plurality of memory banks. Access is caused to be prevented to at least one of the plurality of memory banks while a debug mode or recovery mode is occurring. Also, access is caused to be prevented to the at least one of the plurality of memory banks starting with initial boot until a verification by a security complex is successful. The verification by the security complex includes the security complex verifying a signature.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: George Thomas Letey, Douglas L. Stiles, Edmund B. Nightingale
  • Patent number: 10775874
    Abstract: A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 15, 2020
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Xiaojie He, Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming So, Felix Yat-Sum Ho, Biao Zhou
  • Patent number: 10754662
    Abstract: A method, computer program product, and computing system for initiating a boot mode process for a plurality of devices included within a device cluster of a storage system. The boot mode process includes: generating a cluster device identifier for a first device chosen from the plurality of devices, generating a cluster device count for the first device, and broadcasting from the first device to all of the other plurality of devices, a boot cluster device message. The boot cluster device message includes the cluster device identifier of the first device, and the cluster device count of the first device. The boot cluster device message is broadcast at a first frequency.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Yongquan Yuan, Yong Wang, Zhenzan Zhou
  • Patent number: 10749535
    Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Reuben P. Nelson, Neil E. Weeks
  • Patent number: 10732690
    Abstract: Broadly speaking, the present techniques provide methods, apparatus and systems for monitoring operation of a device. More particularly, the present techniques provide methods for monitoring operation of a device by observing state transitions which occur during the running of a device process following a firmware update, and either comparing the observed state transitions to a state transition map generated within the device or comparing the observed state transitions to a state transition model in, or associated with, the firmware update.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 4, 2020
    Assignee: Arm IP Limited
    Inventors: Niklas Lennart Hauser, Brendan James Moran, Milosch Meriac
  • Patent number: 10732700
    Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 4, 2020
    Assignee: Eta Compute, Inc.
    Inventors: Paul Murtagh, Gopal Raghavan
  • Patent number: 10733131
    Abstract: In some examples, to define a connection path of an initiator to target ports of a plurality of controller nodes that manage access of data in a storage system, a provisioning system determines loads of respective sets of target ports, and selects a selected set of target ports from among the sets of target ports for inclusion in the connection path based on the determined loads.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sudheer Vanapalli, Krishna Babu Puttagunta, Rupin T. Mohan, Vivek Agarwal
  • Patent number: 10725946
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Wade Andrew Butcher
  • Patent number: 10725959
    Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 28, 2020
    Assignee: Analog Devices Global Unlimited Company, Inc.
    Inventors: David Aherne, Jofrey Santillan, Wes Vernon Lofamia, Paul O'Sullivan, Padraig McDaid
  • Patent number: 10725942
    Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 28, 2020
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi N. Kurlagunda, Kenneth K. Chan, Ravi Sunkavalli
  • Patent number: 10719463
    Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Mark Bradley Davis, Matthew Shawn Wilson, Uwe Dannowski, Yaniv Shapira, Adi Habusha, Anthony Nicholas Liguori
  • Patent number: 10719471
    Abstract: Provided is a storage system in which a switch is logically divided into a plurality of partitions including: a plurality of first partitions which are coupled to a plurality of master devices of a processor unit and to which none of storage devices are coupled; and one or more second partitions which are coupled to a plurality of storage devices and which are not coupled to the processor unit. The switch has an address conversion function which is a function for enabling transfer between different partitions. A virtual master device is provided to each of the second partitions. With respect to each of the second partitions, the virtual master device in the second partition executes initial setting with respect to each of all storage devices coupled to the second partition.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 21, 2020
    Assignee: HITACHI, LTD.
    Inventors: Midori Kurokawa, Yuta Yamasaki
  • Patent number: 10719117
    Abstract: The present control apparatus includes a timer for measuring a predetermined time and a clock generation circuit for supplying a clock to a peripheral device. Furthermore, the control apparatus includes a CPU for alternatingly stopping and restarting driving of the clock generation circuit based on the measuring of the predetermined time performed by the timer. On the other hand, the peripheral device includes an interrupt mask that restricts output of an interrupt signal to the control apparatus via the peripheral bus. When the driving of the clock generation circuit is to be stopped, the control apparatus sets the interrupt mask, and when the driving of the clock generation circuit is to be restarted, the control apparatus cancels the interrupt mask.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 21, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keigo Goda
  • Patent number: 10714159
    Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 10705588
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells