Abstract: An information handling system includes a system processor including a first Universal Serial Bus (USB) host interface, a service processor including a second USB host interface and a USB device interface, and a USB socket. The service processor couples a first USB device that is plugged into the USB socket to the first USB host interface, couples a second USB device that is plugged into the USB socket to the second USB host interface, and couples a third USB device that is plugged into the USB socket to the USB device interface.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the plurality of processing cores designates the default processing core to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to generate alternate core IDs that are different from the default core IDs. One of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

Abstract: Examples of the disclosure safely share universal service bus (USB) devices with peripheral component interconnect (PCI) passthrough, and share devices in the USB hierarchy. An in-use counter is maintained for the USB bus and/or for USB hubs. The in-use counter is checked and adjusted when a VM or entity claims and/or unclaims a device. For example, when a PCI passthrough of a USB host controller device is requested, the global in-use counter is checked to determine whether to grant the request. When a VM or entity requests to claim a USB hub, the in-use counter is checked to determine whether to grant the request. The in-use counter indicates whether any USB device attached has been claimed and/or whether the USB host controller device has been claimed by a PCI passthrough operation.

Abstract: A system includes an input/output adapter that includes a multi-source selector coupled to a flow-through input, an elastic first-in-first-out (FIFO) structure, a completion queue, and an output bus. A controller is operatively connected to the input/output adapter. The controller is operable to select the flow-through input to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure is empty. The elastic FIFO structure is selected to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure includes at least one entry. The completion queue is selected to pass through the multi-source selector to the output bus based on determining that the completion queue includes at least one entry. The flow-through input is routed into the elastic FIFO structure based on the completion queue being selected to pass through the multi-source selector to the output bus.

Abstract: A tablet cover (100) and circuitry (400) provide for convenient connection of a tablet (105) or other personal electronic device to additional memory, functions, and features as provided by an internal device (215) and/or an external device (160). The circuitry selectively connects the tablet, the external device, and the additional memory together. The additional memory is internal to the case and is thereby protected from loss or damage due to accidental impact.

Abstract: A portable device provided includes a main processor, an IO processor, a channel port coupled between the main processor and the IO processor, and at least one I/O component coupled to the IO processor. The channel port includes a plurality of channels. The main processor and the IO processor are configured to occupy one of the channels for transmitting a first command therebetween and release the occupied channel after a process is performed according to the first command.

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

Abstract: Disclosed is system, apparatus and method for centralized management of security inspection devices, which provide connection and communication between local security inspection devices and a remote control site according to bus communication scheme. The system comprises: a plurality of security inspection devices arranged on the spot; a remote control site arranged at a remote side; and a field bus network connecting the plurality of security inspection devices with the remote control site and transmitting signals between the plurality of security inspection devices and the remote control site according to bus communication scheme. With implementations of the present invention, correct and reliable centralized management of local security inspection devices from the remote control site can be achieved with less signal lines and simpler layout of the lines.

Abstract: Various embodiments of systems and methods to efficiently use a compute element to process a plurality of values distributed over a plurality of servers using a plurality of keys. In various embodiments, a system is configured to identify (or “derive”) the various server locations of various data values, to send requests to the various servers for the needed data values, to receive the data values from the various servers, and to process the various data values received. In various embodiments, requests are sent and data values are received via a switching network. In various embodiments, the servers are organized in a key value store, which may optionally be a shared memory pool. Various embodiments are systems and methods with a small number of compute elements and servers, but in alternative embodiments the elements may be expanded to hundreds or thousands of compute elements and servers.

Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

Abstract: A method of an embodiment enables locking of downstream ports of a USB hub controller in an electronic apparatus. The method includes the determination step, the assertion step and the lock step. The determination step determines, with a BIOS, whether a lock setting has been made on each of the downstream ports. The assertion step performs, with the BIOS, assertion control for resetting the USB hub controller. The lock step performs, with the BIOS, lock control during the assertion control based on whether the lock setting has been made.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: Systems and methods to share a plurality of virtual network interface controllers (vNICs) amongst a plurality of hosts 104 are described. The described methods are implemented in a network sharing system (NISS) (102) including a programmable vNIC cluster (204) comprising the plurality of vNICs, where a set of vNICs from amongst the plurality of vNICs is dynamically configured to communicate with a host (104-1) from amongst the plurality of hosts (104). Further, the NISS (102) includes a multi-host peripheral component interconnect (PCI) express (PCIe) interface and mapper (MHIP) (202) coupled to the programmable vNIC cluster (204), to receive data packets from the set of vNICs, wherein the set of vNICs comprises one or more vNICs; and provide the data packets from the set of vNICs to the host (104-1) based on demultiplexing of the data packets.

Abstract: A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated.

Abstract: A data processing device includes a first sub-arbiter configured to arbitrate an access by first and second masters that access data stored in a memory; a second sub-arbiter configured to arbitrate an access to the memory by a plurality of masters other than the first and the second masters; a main arbiter configured to prioritize the access to the memory by the first sub-arbiter over the access to the memory by the second sub-arbiter; and a limiting unit configured to limit an amount of the access to the memory by the second master within a preset range.

Abstract: Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. AnHBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.

Abstract: A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.

Abstract: Dynamic lane management for interference mitigation is disclosed. In one aspect, an integrated circuit (IC) is provided that employs a control system configured to mitigate electromagnetic interference (EMI) caused by an aggressor communications bus. The control system is configured to receive information related to EMI conditions and adjust which lanes of the aggressor communications bus are employed for signal transmission. The IC includes an interface configured to couple to the aggressor communications bus. The interface is configured to transmit signals to and receive signals from the aggressor communications bus. The control system is configured to use the information related to the EMI conditions to assign signals to be transmitted via particular lanes of the aggressor communications bus to mitigate the EMI experienced by a victim receiver. The control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to EMI.

Abstract: Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.

Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.