Patents Examined by Reba I. Elmore
  • Patent number: 9626124
    Abstract: A multi-port data storage device that can be used simultaneously by both a direct-attached device and a network-attached device, comprising a hard disk drive (HDD), a DAS port, an NAS port, and a controller for controlling access to the HDD by the DAS port and the NAS port.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: April 18, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Greg J. Lipinski, Phillip M. Walker, Fred Charles Thomas
  • Patent number: 9612949
    Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 4, 2017
    Assignee: ARM LIMITED
    Inventors: Oskar Flordal, Hakan Persson, Andreas Engh-Halstvedt
  • Patent number: 9577932
    Abstract: Techniques for managing ternary content-addressable memory (TCAM) in a network device/system are provided. In one embodiment, the network device/system can include one or more TCAMs and can execute a TCAM manager for each TCAM. Each TCAM manager can manage allocation of resources of its associated TCAM, as well as manage access to the TCAM by one or more network applications running on the device/system. In this way, the TCAM managers can hide TCAM implementation differences (e.g., different sizes, different capabilities, etc.) from the network applications and thereby enable the applications to interact with the TCAMs in a uniform manner.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 21, 2017
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Anil Kumar Ravipati, Prabhat Singh, Chirdeep Panduranga, Prateek Tambi
  • Patent number: 9569139
    Abstract: Methods and apparatus to provide, in a cloud infrastructure environment a shared storage service with only storage, wherein the storage can be shared with other managed services. The storage is exposed to hosts with commands to the storage, networking, and compute resources.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 14, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Stephen A. Mendes, Anurag Jain, Kiran Karnam, Sukesh Kumar Biddappa, Jeffrey B. Gibson
  • Patent number: 9535849
    Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 3, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Mark D. Hummel, Stephen D. Glaser
  • Patent number: 9489309
    Abstract: A system and method for providing a cache virtual partition to a data structure that includes receiving, at an address remapping device, a cache-check request including a memory address including bits, identifying, using a virtual partition table, the virtual partition by determining that the memory address falls within a data structure memory address range, obtaining a copy of virtual partition bits which include a portion of the bits, appending the copy of the virtual partition bits to the memory address, rewriting the virtual partition bits to obtain rewritten virtual partition bits corresponding to the virtual partition, and generating a remapped memory address by replacing the virtual partition bits with the rewritten virtual partition bits. The remapped memory address includes the copy of the virtual partition bits and rewritten virtual partition bits. The method also includes transmitting a remapped cache check request including the remapped memory address to the cache.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 8, 2016
    Assignee: Oracle International Corporation
    Inventors: Pranay Koka, Herbert Dewitt Schwetman, Jr., Mohammad Zulfiqar, Jeff Diamond
  • Patent number: 9477418
    Abstract: Provided are a computer program product, system, and method for assigning device adaptors to use to copy source extents in source ranks to target extents in target ranks in a copy relation. A determination is made of an order of the target ranks in the copy relation. Target ranks in the copy relation are selected according to the determined order. For each selected target rank, indication is made in a device adaptor assignment data structure of a source device adaptor and target device adaptor of the device adaptors to use to copy the source rank to the selected target rank indicated in the copy relation, wherein indication is made for the selected target ranks according to the determined order. The source ranks are copied to the selected target ranks using the source and target device adaptors indicated in the device adaptor assignment data structure.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Theresa M. Brown, Lokesh M. Gupta, Carol S. Mellgren
  • Patent number: 9465669
    Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 11, 2016
    Assignee: VMware, Inc.
    Inventors: Rajesh Venkatasubramanian, Puneet Zaroo, Alexandre Milouchev
  • Patent number: 9454333
    Abstract: Embodiments of the invention provide parity logs for raid systems with variable-capacity media. In one embodiment, a system includes a first set of data storage media devices having variable capacity. The storage devices include a data portion of a parity data set for storing write data being striped to the first. The system further includes a second set of data storage media devices having variable capacity. The second set includes a linear address space of blocks for storing a parity portion of the parity data set. The linear address space is written in a log form. The first and second sets comprise at least one array in a RAID configuration. The system writes the parity portion of the parity data set to the second set, which enables each storage device among the first set to be written to full capacity.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Veera W. Deenadhayalan, Steven R. Hetzler, Wayne C. Hineman, Robert M. Rees, Pin Zhou
  • Patent number: 9454314
    Abstract: A cloud storage system is described. The system includes at least one virtual server comprising at least one virtual storage device, at least one physical machine which includes at least one physical storage device having a data structure stored thereon. The data structure includes a first table of contents associated with a first virtual storage device, and a second table of contents associated with a second virtual storage device. The second virtual storage device is a copied snapshot of the first virtual storage device. The second table of contents is configured to map storage locations within the virtual storage device to node structures that provide pointers to corresponding storage locations with the physical storage device. At least some of the node structures and storage locations are shared by the first and second tables of contents.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 27, 2016
    Assignee: ProfitBricks, Inc.
    Inventors: Conrad N. Wood, Achim Weiss
  • Patent number: 9448935
    Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 20, 2016
    Assignee: NVIDIA Corporation
    Inventors: Jeff Bolz, Patrick R. Brown, Steven J. Heinrich, Dale L. Kirkland, Joel McCormack
  • Patent number: 9451023
    Abstract: Software, firmware, and systems are described herein that create and use a non-production copy of a virtual machine for reverting or restoring the virtual machine. The virtual machine is associated with an external storage device via a logical mapping. A snapshot is taken of a virtual disk associated with the virtual machine to create a snapshot copy of the virtual disk. A snapshot is taken of at least a portion of the mapped external storage device to create a snapshot copy of the mapped external storage device. The snapshot copy of the virtual disk is associated with the snapshot copy of the mapped external storage device. The snapshot copies can then be used to either revert or restore the virtual machine.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 20, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Ashwin Gautamchand Sancheti, Rahul S. Pawar
  • Patent number: 9442852
    Abstract: A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, David W. Cummings, Michael S. Siegel, William J. Starke, Jeff A. Stuecheli
  • Patent number: 9417822
    Abstract: The present invention is directed to systems and methods for the automatic management of volumes, such as creation, migration, and rebuilding for redundant array of independent disks (RAID). The automated management is triggered upon the installation of a new drive in a network attached storage (NAS) device and proceeds according to a user-specified setting. The management is automatic in that user intervention would not be required or requested and would be triggered transparently upon the insertion of a new drive into the NAS device. The embodiments may be employed in other types of multi-drive devices, such as direct attached storage devices, storage area networks, external drives. In addition, the embodiments may be employed with different types of storage media, such as solid-state drives, hybrid drives, etc., in addition to hard disk drives.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 16, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventor: Gary E. Ballance
  • Patent number: 9411871
    Abstract: Responsive to an instruction to collapse a derivative version of an ancestor data volume into the ancestor data volume, it is determined if a characteristic of the derivative version of the ancestor data volume satisfies a criteria relative to a characteristic of the ancestor data volume. If the characteristic of the derivative version satisfies the criteria, the ancestor data volume is merged into the derivative version of the underlying data to form an updated derivative version. The updated derivative version is established as the ancestor data volume.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 9, 2016
    Assignee: Quantum Corporation
    Inventors: Gregory L. Wade, J. Mitchell Haile
  • Patent number: 9405701
    Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 2, 2016
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Weissmann, Karthikeyan Karthik Vaithianathan, Yoav Zach, Boris Ginzburg, Ronny Ronen
  • Patent number: 9405623
    Abstract: There is provided a method of recovering configuration metadata from an erasure encoded RAID array. The RAID array includes raw data including a plurality of codewords encoded using Reed-Solomon encoding. The codewords include message data and checksum data, and the configuration metadata includes parameters relating to the layout of the RAID array. The method includes reading, from the RAID array, raw data including message data and checksum data. Then a set of linear equations are defined using the message data and checksum data. The linear equations are then solved and then, from the solved linear equations, one or more parameters relating to the layout of the RAID array are determined.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: August 2, 2016
    Assignee: Xyratex Technology Limited
    Inventor: Eugene Mathew Taranta, II
  • Patent number: 9405485
    Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 2, 2016
    Assignee: SILICONMOTION INC.
    Inventors: Chun-Kun Lee, Wei-Yi Hsiao
  • Patent number: 9405705
    Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Michael Shachar, Barak Rotbard, Oren Golov, Uri Perlmutter, Dotan Sokolov, Julian Vlaiko, Yair Schwartz
  • Patent number: 9396141
    Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa