Abstract: In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.

Abstract: A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a plurality of data tables constituted with prescribed storage capacity, is stored in a plurality of modification registers. Prescribed address data of one of the plurality of modification registers is selected based on the instruction word. The effective address for addressing the operand is obtained by adding the prescribed address data of the one of the plurality of modification registers to address data included in the operand address. The address data included in the operand address designates addresses which correspond to addresses of the plurality of data tables.

Abstract: A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance. During memory address generation operations, an arithmetic-logic unit (ALU) generates memory addresses from data in a general purpose register (GPR). Then, the memory addresses are written back to the GPR and a memory address register (MAR). During memory access operations, the MAR is accessed for the memory addresses to access a memory. Two approaches are provided. In a first approach, use of the MAR during the memory access operations is explicit. In a second approach, use of the MAR during the memory access operations is transparent. According to the second approach, a controller is provided to validate the MAR during the memory access operations.

Abstract: A Single Inline Memory Module (SIMM) support system enables a computer system to recognize and address 1-Mbyte, 4-Mbyte and 16-Mbyte SIMMs installed in a receiving socket having only a number of pins sufficient to address the 1-Mbyte and 4-Mbyte SIMMs. The capacity of the SIMM is determined by a TYPE signal on a predetermined pin of the installed SIMM which is connected to a pull-up resistor of the SIMM support circuitry and generates a TYPE signal. If the TYPE signal is a logic low, the installed SIMM has a 1-Mbyte capacity. If the TYPE signal is a logic high, the installed SIMM has a 4-Mbyte or a 16-Mbyte capacity. In order to remain pin compatible with 1-Mbyte and 4-Mbyte SIMMs, a 16-Mbyte SIMM cannot have any additional pins to address the additional memory locations. Thus, the TYPE signal shares a pin with the most significant address bit required to address the 16-Mbyte SIMM.

Abstract: A machine translation system includes a translation processor, a display, and a display controller. The display has original and translated sentence display sections. The display controller has a display managing section and a display format controller. The translation processor translates a given original sentence by accessing a dictionary. The translated and original sentences are displayed in the translated and original sentence display sections, i.e., right and left display sections of the display. The original and translated sentences are managed by the display magaging section in predetermined units of translation processing. The display format controller controls the original and translated sentences such that start lines of a given group thereof are horizontally aligned with each other.

Abstract: An associative memory having an associativity of 2.sup.q, where (q) is an integer greater than or equal to one, is provided for storing information relating to data. The memory includes (n) tables, each having a plurality of entries for storing signals associated with data descriptors having a common set portion and common other portions. The entries of table (k), where (k) represents successive integers between (1) and (n-1), store pointers to respective entries of table (k+1). The entries of table (1) are arranged for access as a function of the common set portion and the common portion (1) with which they are respectively associated. The entries of the other tables are arranged for access as a function of (i) a value of the common set portion, (ii) a value of a pointer-respresentative signal of the respective table (m-1) entry means, and (iii) the value of the common portion(m) with which such table(m) entry means is respectively associated.

Abstract: A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation lookaside buffer (TLB) that takes one clock phase to perform this function. The TLB only needs the upper 20 bits of a logical address, which bits correspond to the logical page number, to do the translation to a physical address. The lower 12 bits are not needed until the TLB translation is done. The add of the "base-plus-displacement/offset" usually does not cross a page boundary, that is, the upper 20 bits are the same after the add. A mechanism takes this into account and guesses that the upper 20 bits will not change, and sends them to the TLB. In parallel with the TLB translation, the effective address add of the "base-plus-displacement" is computed.

Abstract: An improved digital packet switching apparatus enabling enhanced packet transmission and high bandwidth packet transfer. The digital packet switching methods and apparatus permit selectively switching digital signal packet between a set of nodes. The invention includes multiple processing cells, each having a processor coupled to an associated content-addressable memory element. Packet processors, electrically coupled to the memory elements, selectively receive packets from the nodes and transmit the packets into at least one of the plural memory elements; or receive packets from the memory elements and transmit the packets to at least one of the nodes.

Abstract: In a computer system having a main storage equipment comprising a plurality of storage equipments, the storage area of each storage equipment is divided in fixed units and an interleave mode is set for each of fixed nuts. When configuration of the main storage equipment is to be changed by disconnection or coupling of storage equipments, necessary data are moved and the interleave mode is changed for all data of the above described fixed unit.

Abstract: A direct memory access (DMA); controller for controlling data transfer between a memory and an input/output (I/O) device comprises an address counter for counting an address to be supplied to the memory, and a read/write controller for controlling a read/write operation between the memory and the I/O device. A jump start address register is provided to hold a jump start address, and an address comparator compares a content of the address counter with a content of the jump start address register. When the address comparator detects consistence between the content of the address counter and the content of the jump start address register, the read/write controller operates to stop the read/write operation between the memory and the I/O device.

Abstract: The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under th

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A predetermined number of logical page addresses are effectively translated into corresponding real ones. The number of the logical page addresses is determined by (M+N) bits and, each of the logical page addresses includes upper M-bit and lower N-bit. Logical page address registers, whose number is equal to 2.sup.N, are provided to respectively store the predetermined number of logical page addresses applied. Address translation buffers (whose number is also equal to 2.sup.N) each stores 2.sup.M real page addresses which are grouped according to each of the lower N bits. The address translation buffers receive the upper M-bit of one of the logical page addresses, and output real addresses. An address translation controller receives the outputs of the address translation buffers and also receives the lower N-bit, and selects the real page addresses using the lower N-bit. The selected real page addresses are applied to a plurality of real address registers.

Abstract: A digital data processing apparatus has plural processing cells, each with a memory element that stores data page made up of plural subpages. At least one of the cells includes a CPU that can request access to a data subpage. A memory manager responds to selected data access requests by (i) allocating, within the memory local to the requesting CPU, exclusive physical storage space for a data page associated with the requested subpage, and (ii) storing the requested subpage in that allocated space. The apparatus recombines data pages and deallocates them on the basis of usage and access state. The apparatus also accesses data asynchronously with respect to execution of instructions by the CPU.

Abstract: A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder.

Abstract: In a memory access control device (10) for use in controlling access by at least one address signal to a memory device (11) comprising memory modules each of which comprises a plurality of memory banks, a module checking circuit (16) checks first and second module signals indicative of the memory modules to produce a module coincidence signal when the first and the second module signals coincide with each other. First and second bank access checking circuits (17, 18) are assigned with first and second preselected number of memory modules and check first and second bank address signals indicative of the memory banks and first and second bank access held signals indicative of at least two of the memory banks which should be accessed. The first and the second bank access checking circuits produce first and second bank coincidence signals when the first and the second bank address signals coincide with the first and the second bank access held signals.

Abstract: A server to which clients subscribe for on-the fly notice of alterations to files and directories in a computer having an operating and file management system. The server also provides status of the execution state of executable code, alteration detection for multiple requests from multiple clients, and tracks files and directories on a user's local station. In addition, the server monitors network-mounted files on remote computers even though events are only generated for local activity on network files.

Abstract: A system for clearing a memory of a virtual machine stores a clearing program for clearing a memory of a virtual machine in a memory area of the virtual machine in response to a request for clearing a memory area assigned to the virtual machine, operates the clearing program on the virtual machine; and clears the memory area portion of the virtual machine in which the clearing program is stored, after a completion of the clearing program. The clearing program is caused to operate on the virtual machine which is the subject of the clear operation and the memory area assigned to the virtual machine is cleared.

Abstract: In accordance with the present invention, by interleaving two banks of memory output registers, a memory system is provided which allows an indefinite number of sequential accesses to contiguous locations of the memory system, requiring only a reduced access time per output datum after the first initial access, regardless of whether row address boundaries are crossed.

Abstract: A memory access control system is disclosed. In this system, a CPU, a low speed memory, a high speed memory and direct memory access controller (DMAC) are connected to a system bus. A high speed memory is connected through a local bus to the CPU. A control circuit is connected to the local bus, the system bus and the high speed memory. A bidirectional buffer is connected to the local and system buses. When the CPU accesses the high speed memory, the control circuit addresses the high speed memory and disables the buffer. As a result, data can directly be transferred between the CPU and the high speed memory. When the CPU accesses the low speed memory, the control circuit drives the system bus according to a protocol of the system bus, thereby to address the low speed memory and enables the buffer. As a result, data can be transferred between the CPU and the low speed memory, via a route of the local bus, the buffer and the system bus.