Abstract: In a method, a mask is formed on a microstructure over a substrate. The mask includes a first pattern over a first region of the microstructure and a second pattern over a second region of the microstructure. A first etching process is performed to etch the microstructure by providing an etching gas and applying a first bias voltage to the substrate according to the first and second patterns of the mask. A protective layer is subsequently formed by providing a deposition gas and applying a second bias voltage to the substrate to cover the first pattern of the mask. A second etching process is performed to transfer the second pattern of the mask further into the second region of the microstructure. The deposition gas has a higher carbon to fluorine ratio than the etching gas, and the second bias voltage is smaller than the first bias voltage.

Abstract: A method for locally annealing and crystallizing a thin film by directing ultrashort optical pulses from an ultrafast laser into the film. The ultrashort pulses can selectively produce an annealed pattern and/or activate dopants on the surface or within the film.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A chip tampering detector is disclosed. The chip tampering detector includes a plurality of resistor-capacitor circuits. Each resistor-capacitor circuit includes a capacitor having a planar area that covers a sensitive area of an integrated circuit of the chip. The resistor-capacitor circuits can be probed with an input signal to generate output signals. The output signals can be measured to determine respective time-constants resistor-capacitor circuits. Tampering with a chip can alter the capacitance of a capacitor covering a sensitive area. Accordingly, a significant change of a time-constant of one or more of the resistor-capacitor circuits can be used to detect chip tampering.

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: A light-emitting device 100 includes: a light-emitting element; a light-transmissive member covering the light-emitting element; and a light-diffusing agent contained in the light-transmissive member and comprising hollow particles. The light-transmissive member has a first surface having irregularities according to the light-diffusing agent. The first surface of the light-transmissive member has a convex shape with a height gradually increased from a peripheral portion of the first surface toward a central portion of the first surface.

Abstract: The present invention provides a method for removing re-sputtered material on a substrate. A process chamber having a plasma source and a substrate support is provided along with the substrate having an upper surface and a lower surface. A masking material having a patterned sidewall is patterned onto the upper surface of the substrate along with a sacrificial layer between the upper surface of the substrate and the masking material. The lower surface of the substrate is placed onto the substrate support. A plasma is generated using the plasma source. The substrate is processed on the substrate support using the generated plasma. The sacrificial layer is removed after the processing of the substrate.

Abstract: The present technology relates to a semiconductor device and an electronic apparatus that make it possible to suppress the generation of noise in signals. A semiconductor device includes: a first semiconductor substrate on which at least a portion of a first conductor loop is formed; and a second semiconductor substrate on which a second conductor loop is formed. The second semiconductor substrate includes a first conductor layer and a second conductor layer. The first conductor layer and the second conductor layer each include a conductor. The first conductor layer and the second conductor layer are configured to cause a direction of a loop surface in which a magnetic flux is generated from the second conductor loop to be different from a direction of a loop surface in which an induced electromotive force is generated in the first conductor loop. The present technology is applicable, for example, to a CMOS image sensor.

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods for activating a p-type dopant in a group III-Nitride semiconductor are provided. In embodiments, such a method comprises annealing, in situ, a film of a group III-Nitride semiconductor comprising a p-type dopant formed via metalorganic chemical vapor deposition (MOCVD) at a first temperature for a first period of time under an atmosphere comprising NH3 and N2; and cooling, in situ, the film of the group III-Nitride semiconductor to a second temperature that is lower than the first temperature under an atmosphere comprising N2 in the absence of NH3, to form an activated p-type group III-Nitride semiconductor film.

Abstract: There is provided a technique that includes: (a) arranging a plurality of first substrates and a second substrate having a smaller surface area than the first substrates and accommodating the plurality of first substrates and the second substrate in a process chamber; and (b) forming a thin film on each of the plurality of first substrates by supplying a processing gas to a substrate arrangement region in which the plurality of first substrates and the second substrate are arranged, wherein (b) includes: (c) supplying a dilution gas to a first supply region of the substrate arrangement region, or not performing a supply of the dilution gas to the first supply region, and supplying the dilution gas to at least one second supply region of the substrate arrangement region at a flow rate larger than a flow rate of the dilution gas supplied to the first supply region.

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a metal oxide layer is formed over the gate insulating layer, and a gate electrode which overlaps with part of the semiconductor layer is formed over the metal oxide layer. Then, a first element is supplied through the metal oxide layer and the gate insulating layer to a region of the semiconductor layer that does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon. The metal oxide layer may be processed after the first element is supplied to the semiconductor layer.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.