Abstract: The present invention provides a method for managing memory space in an electronic device including: selecting a candidate page from a first memory space for swapping the candidate page out of the first memory space into the second memory space; compressing the candidate page to obtain a first compressed page and a first hash value of the first compressed page; performing a comparison using the first hash value of the first compressed page and the hash values of the pages stored in a second memory space to find whether the pages have the same content as the first compressed page or the candidate page; and if a page is found to have the same content as the first compressed page or the candidate page, mapping a virtual address of the first compressed page or the candidate page to the found page.

Abstract: A method for securely removing data from a storage system is disclosed. In one embodiment, such a method includes receiving, by a storage system, instructions to erase logical units from the storage system. In response to receiving the instructions, the storage system maps the logical units to physical extents on the storage system. The storage system then initiates, using at least one of hardware and software embedded in the storage system, a secure data removal process that securely erases data from the physical extents by overwriting the data thereon, while leaving intact data stored on other physical extents of the storage system. The storage system is configured to process I/O to the other physical extents during execution of the secure data removal process. A corresponding system and computer program product are also disclosed.

Abstract: Methods, systems and computer-readable storage media for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.

Abstract: Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller reads write data associated with a first write command from a host memory by a unit of a first size in response to the first write command from a host. The host memory is included in the host. In a case where the size of first data not yet read from the host memory out of the write data is less than a second size, in response to a second write command, the controller reads second data of the second size and writes the read second data into the nonvolatile memory. The second data includes the first data and third data included in write data associated with the second write command. After writing the second data into the nonvolatile memory, the controller transmits a notice for the first write command to the host.

Abstract: A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing storage devices. In some implementations, a memory controller receives a logical write request over a logical interface that the memory controller provides for accessing a non-volatile storage device. The logical write request indicates a logical address at which to write data to the non-volatile storage device. In response to receiving the logical write request, the memory controller sends a write request event to a host system. The memory controller receives a physical write command from the host system over a physical interface that the memory controller provides for accessing the non-volatile storage device. In response to receiving the physical write command, the memory controller stores the data in the non-volatile storage device according to the physical write command.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced.

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract: A system, method, and computer program product for managing storage volumes in a point-in-time copy cascade. A processor swaps a host portion of a source volume with a host portion of a snapshot point-in-time copy volume. Responsive to an I/O request to overwrite a first data value in a grain of the source volume with a second data value, a processor writes the second data value in a corresponding grain of the snapshot point-in-time copy volume. Responsive to a corresponding grain of a clone point-in-time copy volume not comprising the first data value, a processor copies the first data value to the corresponding grain of the clone point-in-time copy volume.

Abstract: Methods for protecting data on an integrated circuit including a memory are described. One method includes storing nonvolatile protection codes on the integrated circuit. The nonvolatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in a plurality of sectors of the memory. The method includes storing volatile protection codes on the integrated circuit. The volatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in the plurality of sectors. The method includes blocking modification in a particular sector using circuitry on the integrated circuit when the volatile protection code for the particular sector has the first value, else allowing modification in the particular sector, and setting the volatile protection codes to values of the nonvolatile protection codes in an initialization procedure.

Abstract: An illustrative pseudo-file-system driver uses deduplication functionality and resources in a storage management system to provide an application and/or a virtual machine with access to a locally-stored file system. From the perspective of the application/virtual machine, the file system appears to be of virtually unlimited capacity. The pseudo-file-system driver instantiates the file system in primary storage, e.g., configured on a local disk. The application/virtual machine requires no configured settings or limits for the file system's storage capacity, and may thus treat the file system as “infinite.” The pseudo-file-system driver intercepts write requests and may use the deduplication infrastructure in the storage management system to offload excess data from local primary storage to deduplicated secondary storage, based on a deduplication database.

Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.

Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Abstract: A method is provided for cache coherence being based on a hybrid approach relying on hardware-and software-implemented functionalities. In case a processor core is requested to perform a write operation on a memory line missed in the local cache of said core, a hardware-implemented coherence directory ensures that said processor core becomes assigned exclusive write permissions to indicate that the memory line in said local cache is up-to-date after said write. In case the processor core is requested to perform a read operation on a memory line missed in the local cache of said processor core, the coherence directory updates the coherence directory to indicate that none of the processor cores of the system has exclusive write permission on the memory line and relies on software executed on said processor core to ensure that the cached memory line is up-to-date before performing the read operation.

Abstract: The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, subdividing the first memory block into sections, assigning a binary value to each section, and determining if the first memory block corresponds to the enabled section. An image of the load instruction is obtained and a pointer address is calculated from the image. The object pointer is read and it is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.