Patents Examined by Reginald Bragdon
  • Patent number: 9652389
    Abstract: A coordinating node maintains globally consistent logical block address (LBA) metadata for a hierarchy of caches, which may be implemented in local and cloud based storage resources. Associated storage endpoints initially determine a hash associated with each access request, but forward the access request to the coordinating node to determine a unique discriminator for each hash.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 16, 2017
    Assignee: ClearSky Data
    Inventors: Lazarus Vekiarides, Daniel Suman, Janice Ann Lacy
  • Patent number: 9646039
    Abstract: A system and method for creating and managing snapshots. Mediums are recorded and maintained, all of which are read-only except for the most recent mediums in use by a volume. Multiple volumes may be maintained, including a first volume which points to a first medium. When a snapshot of the first volume is taken, a second medium is created that points to the first medium. The first volume is also updated to point to the second medium. The first medium becomes the underlying medium of the second medium, and lookups are performed initially on the second medium and then on the first medium if the data is not located in the second medium.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 9, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Ethan Miller, John Hayes, Cary Sandvig, Christopher Golden, Jianting Cao
  • Patent number: 9645742
    Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn
  • Patent number: 9645741
    Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn
  • Patent number: 9645929
    Abstract: In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 9, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: James Van Zoeren, Alexander Klaiber, Guillermo J. Rozas, Paul Serris
  • Patent number: 9641378
    Abstract: Storing data from a volatile memory of a host in a non-volatile memory (NVM) of a data storage device (DSD). Data from the volatile memory of the host is identified which has been compressed with a first compression ratio. The identified data is decompressed and a second compression ratio is determined based on a time to restore the data to the volatile memory of the host and characteristics of the NVM. At least a portion of the decompressed data is recompressed with the second compression ratio and at least a portion of the recompressed data is stored in the NVM.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 2, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: David N. Steffen
  • Patent number: 9639472
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas M. Gooding
  • Patent number: 9639430
    Abstract: Machines, systems and methods for performing intermediate data backups, the method comprising monitoring data updates to one or more data blocks in at least a target data storage medium, wherein the target data storage medium is subject to an incremental data backup routine at prescheduled time intervals; in response to determining that said at least one or more data blocks is updated prior to a prescheduled time interval for the incremental data backup routine, performing one or more intermediate data backups to store data from the updated data blocks to at least one backup data storage medium; and in response to determining that said at least one or more data blocks is updated prior to the prescheduled time interval for the incremental data backup routine but after the last of the intermediate data backups, copying data on one or more updated data blocks after the last of the intermediate data backups to the backup data storage medium.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ofer Peretz, Michael Sternberg, Asaf Yeger
  • Patent number: 9639466
    Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 2, 2017
    Assignee: NVIDIA Corporation
    Inventors: James Patrick Robertson, Gregory Alan Muthler, Hemayet Hossain, Timothy John Purcell, Karan Mehra, Peter B. Holmqvist, George R. Lynch
  • Patent number: 9632791
    Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventors: Muawya M. Al-Otoom, Ian D. Kountanis, Ronald P. Hall, Michael L. Karm
  • Patent number: 9632710
    Abstract: Dynamically manages a creation and a destruction of a plurality of Flashcopy resources and the target volumes using configurable high-water marks and maximum values.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph W. Dain, Gregory T. Kishi, Christopher Zaremba
  • Patent number: 9626294
    Abstract: According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
  • Patent number: 9626114
    Abstract: The invention provides a technique for managing write operations issued to a non-volatile memory included in a wireless device. A monitor software application executes on the wireless device and is configured to determine that a number of write operations issued to the non-volatile memory is greater than or equal to a write operation threshold associated with the non-volatile memory. In response, at least one application is isolated as the application responsible for issuing excessive write operations. The isolation can be carried out locally on the wireless device, or the isolation can be carried out remotely at a server by sending information about the write operations to the server. The monitor then limits additional write operations from being issued to the non-volatile memory so as to protect the non-volatile memory from becoming corrupted or inoperable.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: April 18, 2017
    Assignee: Apple Inc.
    Inventors: Li Li, Ben-Heng Juang, Arun G. Mathias
  • Patent number: 9626296
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas M. Gooding
  • Patent number: 9619398
    Abstract: In one embodiment, a method includes receive a translation vector, selecting a translation entry from a plurality of translation entries, and determining whether the translation entry is associated with a first identifier class or a second identifier class. The translation vector includes a first identifier, a second identifier, and a virtual memory identifier. The first identifier is associated with a first identifier class, and the second identifier is associated with a second identifier class. The translation vector is received from a translation module including a memory configured to store the plurality of translation entries. Each translation entry from the plurality of translation entries including a virtual memory identifier. The translation entry is selected from the plurality of translation entries of the translation module based on the virtual memory identifier of the translation vector.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: April 11, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Xiangwen Xu, Hexin Wang, Xiang Zhu
  • Patent number: 9612914
    Abstract: Techniques for virtualization of file based content are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for virtualization of file based content comprising creating, using at least one computer processor, a virtual disk containing metadata associated with one or more files of a backup image. The techniques may include receiving an Input/Output (I/O) request associated with a file of the one or more files of the virtual disk, determining whether the Input/Output (I/O) request is directed towards a virtual disk location containing a portion of the metadata of the virtual disk or a virtual disk location indicating file data of the backup image, sending the Input/Output (I/O) request to the backup image to the virtual disk based on the determination.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 4, 2017
    Assignee: Veritas Technologies LLC
    Inventor: Srineet Sridharan
  • Patent number: 9612982
    Abstract: Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: April 4, 2017
    Assignees: Beijing Lenovo Software Ltd., Lenovo (Beijing) Limited
    Inventors: Jingang Peng, Xiaogang Wang, Xiaoyi Feng
  • Patent number: 9606911
    Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 28, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Chi-Lung Wang, Chia-Hsin Chen, Chien-Cheng Lin
  • Patent number: 9600202
    Abstract: Disclosed are a method and device for implementing memory migration, which relate to computer technology and are invented for solving the problem that the existing operating process for memory migration is relatively complicated. The technical solution provided in the embodiments of the present application includes: the basic input-output system of a computer migrating the data in the memory to be migrated to a first unavailable memory in the operating system of the computer when migrating the memory to be migrated and the basic input-output system storing the mapping relationship between the memory to be migrated and the physical address of the first unavailable memory. The embodiments of the present application can be applied to ordinary computer systems and computer systems under the NUMA architecture.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: March 21, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xishi Qiu, Wei Wang, Gaohuai Han
  • Patent number: 9600204
    Abstract: A method for collection instance resizing. The method may include identifying at least one collection object within a collection framework of a virtual machine. The method may also include determining the at least one identified collection object satisfies at least one preconfigured criteria. The method may further include determining a garbage collection cycle count associated with the at least one identified collection object exceeds a preconfigured threshold. The method may also include determining an occupancy ratio associated with the at least one identified collection object is less than a preconfigured shrink threshold. The method may further include restructuring the at least one identified collection object based on the at least one identified collection object satisfying the at least one preconfigured criteria, the garbage collection cycle count exceeding the preconfigured threshold, and the occupancy ratio being less than the preconfigured shrink threshold.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Guru C. Ganta, Gireesh Punathil