Abstract: A display device includes a substrate that includes a display area and a transmissive area, a first blocking layer that is disposed on the display area of the substrate, and disposed on a first surface of the substrate, a second blocking layer that is disposed in the display area of the substrate, and disposed on a second surface of the substrate opposite to the first surface, an insulation layer that is disposed on the first blocking layer, a transistor that is disposed on the insulation layer, and a light emitting element that is connected to the transistor.

Abstract: A light-emitting element includes: a cathode; an anode; and an electron-transport layer, a light-emitting layer, and a hole-transport layer provided, between the cathode and the anode, in a stated order from the cathode. At least one of the electron-transport layer or the hole-transport layer includes: a first charge-transport layer and a second charge-transport layer containing different carrier-transport materials. The light-emitting element includes, in plan view, a first region including the first charge-transport layer, and a second region including the second charge-transport layer. The light-emitting element shares the anode and the cathode between the first region and the second region.

Abstract: A display apparatus can include a first subpixel and a second subpixel disposed on a substrate; a first electrode in each of the first subpixel and the second subpixel; a light-emitting layer on the first electrode in each of the first and second subpixels; and a second electrode on the light-emitting layer, in which a structure of the first electrode in the first subpixel is different than a structure of the first electrode in the second subpixel.

Abstract: A display panel and a display apparatus. The display panel includes a first display region and a second display region, an array substrate, a plurality of light-emitting structures, a plurality of pixel driver circuits and at least one isolation structure. The first display region is disposed around at least a portion of the second display region, and the second display region corresponds to a photosensitive device configured to collect light through the second display region. The plurality of light-emitting structures are located on the array substrate and disposed in both the first display region and the second display region. The plurality of pixel driver circuits are disposed in the array substrate, and the plurality of pixel driver circuits are disposed in one-to-one correspondence with the plurality of light-emitting structures.

Abstract: A display device includes: a substrate including an opening area, a display area, and a non-display area arranged between the opening area and the display area; a first thin-film transistor arranged on the substrate and including a first semiconductor layer including a silicon semiconductor; a first insulating layer covering the first semiconductor layer and defining a lower contact hole overlapping the non-display area, a second thin-film transistor arranged on the first insulating layer and including a second semiconductor layer including an oxide semiconductor; a second insulating layer covering the second semiconductor layer and defining an upper contact hole overlapping the lower contact hole; a display element overlapping the display area, a lower conductive layer overlapping the lower contact hole; and an upper conductive layer arranged on the second insulating layer and connected to the lower conductive layer through the lower contact hole and the upper contact hole.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

Abstract: An organic electroluminescent device comprises an anode, a first organic light emitting layer, an exciton control layer, a second organic light emitting layer, and a cathode that are successively stacked, wherein the first organic light emitting layer comprises a hole transport type host material and a first doped material; the exciton control layer is provided on the surface of the first organic light emitting layer away from the anode; the exciton control layer comprises a first hole transport material and a first electron transport material; the second organic light emitting layer comprises an electron transport type host material and a second doped material; the cathode is provided on the side of the second organic light emitting layer away from the anode; and one of the first doped material and the second doped material is a fluorescence-doped material, and the other is a phosphorescence-doped material.

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) and first and second electrodes. The MTJ includes: (a) a first ferromagnetic (FM) layer, configured to have a magnetic spin in a first spin direction, and retain the first spin direction while MTJ subjected to electrical current in first and second directions, (b) a second FM layer, configured to have the magnetic spin selectively altered between the first and second spin direction, in response to altering the electrical current between the first and second directions, respectively, and (c) a stack of tunnel barrier (TB) layers, having: a first TB layer disposed over the first FM layer and having a first morphological structure, and a second TB layer, disposed between the first TB layer and the second FM layer and having a second, different, morphological structure. The first and second electrodes are electrically connected to the first and second FM layers, respectively.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer and a first sacrificial layer are alternately and repeatedly formed on a substrate to form a mold layer. A sacrificial layer structure is formed on the mold layer to include an etch stop layer and a second sacrificial layer sequentially stacked. After forming a hard mask on the sacrificial layer structure, the sacrificial layer structure and the mold layer are etched by a dry etching process using the hard mask as an etching mask to form a channel hole exposing an upper surface of the substrate and form a recess on a sidewall of the second sacrificial layer adjacent to the channel hole. A memory channel structure is formed in the channel hole. The first sacrificial layer is replaced with a gate electrode.

Abstract: A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.

Abstract: A memory device includes a substrate and an eFuse structure. The substrate includes an array region and an eFuse region and the eFuse region of the substrate has an eFuse trench. The eFuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line, and an eFuse gate electrode. The first gate oxide layer is conformally formed on a surface of the eFuse trench. The doped regions are respectively formed in the substrate on opposite sides outside the eFuse trench, and in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The eFuse gate electrode is formed on the dummy buried word line and in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the eFuse gate electrode.

Abstract: According to one embodiment, a semiconductor memory device includes interconnect layers stacked above a substrate; a memory pillar configured to penetrate the interconnect layers; a first member and a second member; and a dividing portion provided between the first member and the second member. The dividing portion includes insulating layers. The insulating layers each include a first portion and a second portion. The first portion is provided between the first member and the second portion. The second portion is provided between the first portion and the second member. The first portion and the second portion each have an individual arc shape when viewed from a top and are in contact with each other.

Abstract: A method of etching an indium gallium zinc oxide (IGZO) structure is provided. In one aspect, the method includes exposing the IGZO structure to a reactant flow including a hydrocarbon-based reactant. Thereby, a reactant layer is formed on the IGZO structure. The method also includes exposing the reactant layer formed on the IGZO structure to an argon flow. Thereby, one or more reactant molecules are removed from the reactant layer. The one or more reactant molecules, which are removed from the reactant layer formed on the IGZO structure, are removed together with one or more IGZO molecules, thus leading to an etching of the IGZO structure.

Abstract: A display device includes: ferritin encaging a first quantum dot and modified with a first peptide bound to a first pixel electrode; and ferritin encaging a second quantum dot and modified with a second peptide bound to a second pixel electrode. A first metal material and a second metal material are of different types.