Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.

Abstract: A magnetoresistive device includes a magnetic free layer having first and second surfaces, the magnetic free layer being comprised of a ferromagnetic material having a perpendicular magnetic anisotropy, a spin current generation layer contacting the first surface of the magnetic free layer, a tunnel barrier layer having one surface contacting the second surface of the magnetic free layer, a reference layer contacting another surface of the tunnel barrier layer, and a leakage field generation layer including first and second leakage field generation layers each of which is comprised of a ferromagnetic material and generates a leakage field, an in-plane component of the leakage field at an part of the magnetic free layer is formed generating a domain wall having an in-plane magnetization component in the magnetic free layer.

Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.

Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.

Abstract: An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and selectively receive a characteristic calibration signal according to an external input, such that characteristics of the input/output terminals corresponding to the characteristic calibration signal are calibrated. The input/output terminal characteristic calibration circuit may also include a characteristic calibration signal generation circuit coupled to the plurality of input/output terminals in common through a test signal line, and configured to provide the characteristic calibration signal to the plurality of input/output terminals in common through the test signal line.

Abstract: A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.

Abstract: Method and apparatus for managing data in a stacked semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, a data set is written to the memory array by programming a stack of memory cells to a desired set of program states. A first set of pulses is applied to verify the memory cells conform to the desired set of program states. The verified stack of memory cells are subsequently conditioned by applying a second set of pulses to remove accumulated charge from a shared channel region of the stack. The conditioning of the memory cells reduces a step-wise increase in the number of read errors during the first read operation as compared to subsequent read operations on the memory cells.

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: According to one embodiment, a semiconductor device includes, for example, a circuit board, a plurality of elements, a plurality of controllers, and a first signal line. The elements are provided on the circuit board. The elements each include a memory. The controllers each are configured to control read of data from the memory. The controllers each are configured to control write of data into the memory. A control signal is transmitted through the first signal line. The first signal line is used in common by the controllers.

Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.

Abstract: An object is to solve all of the following problems caused when a volatile register and a non-volatile register are used as registers in a processor: degradation of the integrity of data stored in the non-volatile register; loss of data security due to the processor and a non-volatile memory device that are provided apart from each other; and slow data processing speed due to wiring delay or the like caused by these devices provided apart from each other. When data maintained in the volatile register is stored in the non-volatile register before supply of power supply voltage is stopped, the data is encrypted by an encryption circuit and stored in a non-volatile memory device that is provided separately from the processor. Then, the data stored in the non-volatile register is compared with the compressed and encrypted data stored in the non-volatile memory device.