Patents Examined by Richard K. Blum
  • Patent number: 4837571
    Abstract: The described circuit arrangement for converting a data signal having a constant bit rate and code words of different length into an output signal consisting of code words of constant length but with a variable bit rate while using a buffer memory comprises a first encoder which recognizes code words of the data signal and converts them into code words of equal length, said code words being written in the buffer memory, read out from this memory by a second encoder and being converted into code words of the output signal. The construction of the first encoder is characterized in that a first EPROM and a comparator are connected to the parallel outputs of a shift register through which the data signal with its bit clock is shifted. The output data of the first EPROM and of the comparator are transferred to an intermediate memory and simultaneously applied to the address inputs of a second EPROM.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: June 6, 1989
    Assignee: U.S. Philips Corporation
    Inventor: Georg Lutz
  • Patent number: 4833472
    Abstract: An arrangement for setting an analog resistor to a value which is digitally predetermined. The arrangement contains a resistor (2) which is variable by a control voltage as setting member of a control circuit, in series with a measurement resistor (3) and a rotary-magnet ratio meter (26). This series connection is fed from an operating voltage. The voltage at the measurement resistor (3) and the digital value are each fed to inputs of a multiplier (5) the outputs of which are connected via a digital/analog converter (6) to an input of a subtraction circuit (7). The other input of the subtraction circuit (7) is acted on by a reference voltage. The output of the subtraction circuit (7) produces the control voltage for the adjustable resistor (2).
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: May 23, 1989
    Assignee: VDO Adolf Schindling AG
    Inventors: Joachim Hannappel, Thomas Pfeifer
  • Patent number: 4831376
    Abstract: The present invention relates to an optical laser analog-to-digital (A/D) converter and the use of such a converter as a transducer. In a first embodiment of the invention, the converter consists of a source which produces a coherent beam of light that is passed through a lens system to produce a line or bar of light. The bar of light passes through a coded optical mask which is made of a thin transparent material with a binary or gray code printed thereon. The mask is mounted to an object whose movement is to be detected. The mask may also be configured in the form of a circle and mounted to a motor shaft to sense motor rotational displacement, RPM or velocity. As the mask moves, the imprinted pattern changes according to the coding on the mask. The portion of the light that passes through the mask strikes the target of a moving recording media.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: May 16, 1989
    Assignee: Center for Innovative Technology
    Inventors: Samuel K. Reid, Dan D. Chen
  • Patent number: 4823128
    Abstract: A digital-to-analog converter filter circuit includes a means for generating a blanking signal to coincide with a change in the digital signal value to the converter and an analog switch controlled by the blanking signal. The analog switch receives the analog signal from the converter and passes the signal depending on the state of the blanking signal. The blanking signal controls the switch to block passage of the analog signal for a predetermined time sufficient for the analog signal to settle after transition from a first value to a second value in response to the change in the digital input signal value. The analog switch is connected to a vector filter which receives the analog signal and transmits a delayed transition signal from the first analog signal value signal to the second value. The filter transmits the first value until the switch passes the second value upon command of the blanking signal.
    Type: Grant
    Filed: May 19, 1986
    Date of Patent: April 18, 1989
    Assignee: Tektronix, Inc.
    Inventor: David T. Barak
  • Patent number: 4819051
    Abstract: An angular position encoder utilizes Moire fringes formed by illuminating regions of coded images arranged circumferentially on wheels rotatable in accordance with angles to be encoded. Movement of the Moire fringes from a reference position is detected and used to determine the angular movement. All non-rotating movements of the coded wheel are compensated by the encoding process and do not effect the output.
    Type: Grant
    Filed: June 29, 1987
    Date of Patent: April 4, 1989
    Assignee: Honeywell Inc.
    Inventor: Peter E. Jacobson
  • Patent number: 4818995
    Abstract: A parallel pulse transmission system, wherein the sending side converts original signals into line coded signals of a block coding type (mBnB line codes, m/2.gtoreq.2/3, n.gtoreq.3) and transmits them after aligning the timings of the blocks receiving side. The regenerates of the systems transmitted line codes and thereafter, aligns the timings of blocks of the line codes.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: April 4, 1989
    Assignees: Hitachi Ltd., Nippon Telegraph and Telephone Corporation
    Inventors: Yoshitaka Takahashi, Yasushi Takahashi, Yukio Nakano, Akihiro Hori, Minoru Maeda, Yoshihiko Miyano, Ikuo Tokizawa, Masatoyo Sumida
  • Patent number: 4816805
    Abstract: Signal processing techniques are disclosed for applications such as finite impulse response filtering. After initial processing in residue number system (RNS) channels, the signals are converted from residue form to a true external representation of the filter output. The conversion employs a chinese remainder theorem decoder and shift accumulator controlled to utilize adaptive modulo reduction. As a consequence, each modulus function value is reduced during computation when it exceeds the modulus and not at the end of the function evaluation. This reduces hardware requirements by minimizing the arithmetic word length. In implementing the technique, each function value is tested to see if it is within a modulus range and the corresponding modulus value is subtracted if it is not. This is done as many times as is necessary to bring each function value within the range.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: March 28, 1989
    Assignee: Grumman Aerospace Corporation
    Inventors: William M. Vojir, Joel R. Davidson
  • Patent number: 4814746
    Abstract: Communications between a Host Computing System and a number of remote terminals is enhanced by a data compression method which modifies the data compression method of Lempel and Ziv by addition of new character and new string extensions to improve the compression ratio, and deletion of a least recently used routine to limit the encoding tables to a fixed size to significantly improve data transmission efficiency.
    Type: Grant
    Filed: August 11, 1986
    Date of Patent: March 21, 1989
    Assignee: International Business Machines Corporation
    Inventors: Victor S. Miller, Mark N. Wegman
  • Patent number: 4814767
    Abstract: A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group.
    Type: Grant
    Filed: October 8, 1987
    Date of Patent: March 21, 1989
    Assignee: Analog Devices, Inc.
    Inventors: John W. Fernandes, Gerald A. Miller, Andrew M. Mallinson
  • Patent number: 4814740
    Abstract: A glitch occurrence prevention circuit for a digital/analog converter comprising semiconductor switching means which is turned on or off in relation to a level between a digital input voltage and a set threshold voltage, but having inconsistent timing of being turned on and off in response to the digital signal due to a switching characteristic of different rise and fall times, the glitch occurrence prevention circuit having means to normally provide a predetermined bias voltage to the digital input of the digital/analog converter so that the timing of turning on and off the semiconductor switching means is consistent.
    Type: Grant
    Filed: March 18, 1987
    Date of Patent: March 21, 1989
    Assignee: Nakamichi Corporation
    Inventor: Kozo Kobayashi
  • Patent number: 4812818
    Abstract: An integrated circuit chip has circuitry for converting a binary coded value to an analog value. The chip includes first and second matrices each defined by rows and columns. The rows and columns have sources at different positions for producing currents in response to binary signals coding for the binary value. Each row in the first matrix is connected to a row in the second matrix on a reverse-image basis. For example, if each matrix has thirty two (32) rows, rows 1 and 32 in the first matrix are respectively connected to rows 32 and 1 in the second matrix. The rows in the matrices are sequentially selected in a pattern providing particular convergences and divergences of successive paris of such rows in each matrix. Such sequential selection provides progressive convergences and then progressive divergences of the rows in each of the successive pairs in each matrix about the center line as a reference. Such progressive convergences and divergences may occur in at least a pair of successive cycles.
    Type: Grant
    Filed: February 24, 1987
    Date of Patent: March 14, 1989
    Assignee: Brooktree Corporation
    Inventor: Joseph H. Colles
  • Patent number: 4812816
    Abstract: In conventional digital-to-analog converters one of a number of multi-emitter transistors is driven by means of the select logics, the emitters of which are connected selectively to a group of data lines. The output circuits connected to the data lines further receive a reference voltage to be able to detect the condition on the data lines. In the analog converter according to the invention each data line is constructed so as to be complementary in which the emitters which in the prior art circuit arrangement are connected to the first group of data lines are coupled in the same manner to a first group of data lines while the remaining emitters are now connected to complementary lines from the second group. The output circuits which are connected to the data lines receive a logic signal of a data line and the complementary logic signal of the associated complementary data line. The result is that the voltage step which is presented to the inputs of the output circuits is twice as large.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: March 14, 1989
    Assignee: U.S. Philips Corporation
    Inventors: Robert E. J. van de Grift, Martien van der Veen
  • Patent number: 4812815
    Abstract: A D/A converter system for converting digital signal to analog signal includes a circuit for converting digital signal such as PCM signal to pulse density modulation signal, and an analog low-pass filter for converting the pulse density modulation signal to analog signal by removing noise from the pulse density modulation signal.
    Type: Grant
    Filed: October 24, 1986
    Date of Patent: March 14, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazumitsu Miyakoshi, Mitsuyoshi Nakaya
  • Patent number: 4811017
    Abstract: This very high resolution digital-to-analog converter has a highest possible conversion speed as its output voltage corresponding to the input code is determined immediately. The converter has an inherent low impedance bipolar output. A digital error correction is optional.In one embodiment the converter includes at least one reference signal source and a first resistor network coupled thereto for providing a plurality of reference voltages. In response to MSBs (or LSBs), a multiplexer selects one of the reference voltages which is applied to noninverting input of an operational amplifier. A second resistor network is coupled between the inverting input and output of the operational amplifier, and has a plurality of inputs each exhibiting a respective resistance to the output of the operational amplifier. A demultiplexer couples a current source to one of the second resistor network inputs in response to LSBs (or MSBs). The conversion result is the output voltage of the operational amplifier.
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: March 7, 1989
    Inventor: Zdzislaw Gulczynski
  • Patent number: 4806907
    Abstract: An apparatus and method for encoding a digital data signal, which apparatus and method converts a digital data signal to a string of truncated and extended pulses, the truncated pulses corresponding to a digital "0" and the extended pulses corresponding to a digital "1". The frequency of the leading edges of all of the pulses in this pulse string is the clock frequency such that a clock signal can be generated by the receiver directly to synchronize the receiver to the transmitter. Further, the trailing edge of the transmitted pulses contain the data information. Specifically, the pulses are varied in length with a truncated pulse corresponding to a digital "0" and an elongated pulse corresponding to a digital "1". A decoding apparatus is also described for decoding the encoded signal to generate a digital signal corresponding to the original data signal to be encoded.
    Type: Grant
    Filed: August 4, 1986
    Date of Patent: February 21, 1989
    Inventor: Leon M. Furgason
  • Patent number: 4804960
    Abstract: A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group.
    Type: Grant
    Filed: October 8, 1987
    Date of Patent: February 14, 1989
    Assignee: Analog Deivces, Incorporated
    Inventors: John W. Fernandes, Gerald A. Miller, Andrew M. Mallinson, Stephen R. Lewis
  • Patent number: 4804959
    Abstract: To increase storage capacity of a disk storage device, the recording surface of the device is partitioned into a plurality of concentric recording bands, data to be recorded on respective bands are encoded using different run-length-limited codes with the code rate of each band being higher than the adjacent inner band.
    Type: Grant
    Filed: November 10, 1987
    Date of Patent: February 14, 1989
    Assignee: International Business Machines Corporation
    Inventors: Tarek Makansi, Constantin M. Melas, Arvind M. Patel, Steven H. Souther
  • Patent number: 4803461
    Abstract: The R-2R type D/A converter comprises an R-2R type D/A converter circuit provided with first and second series circuits each comprising a resistor and a switch. The first series circuit is connected between one end of a ladder resistor circuit and the ground. The second series circuit is connected between the other end of the ladder resistor circuit and the ground. The switches in the first and second series circuits are selectively turned on/off, so that an output signal may be supplied in either direction. First and second analog circuits are connected one to each terminal of the R-2R type D/A converter circuit. By turning on/off the switches of the first and second series circuits, a D/A converted output signal may be supplied selectively to the first or second analog circuit.
    Type: Grant
    Filed: September 16, 1987
    Date of Patent: February 7, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yamaguchi, Toshimasa Kawaai
  • Patent number: 4800365
    Abstract: A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between V.sub.CC and a reference voltage that is adjusted to cause the on resistances of a P-channel "monitor" MOSFET and an N-channel "monitor" MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a V.sub.BE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the V.sub.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: January 24, 1989
    Assignee: Burr-Brown Corporation
    Inventors: Robert L. White, Frederick J. Highton, Kazuo Ito, Gary L. Miller
  • Patent number: 4799043
    Abstract: A circuit resistance adjusting device for producing a combined resistance consisting of a plurality of resistances which are selectively connected by a switching member. The switching member includes a plurality of switching elements and fuses which are respectively connected with the resistances, wherein when a hold signal is applied to the switching member, the fuses are adapted to be fused off. A patterning member sequentially generates a predetermined pattern signal to the switching member on a step-by-step basis when a signal is applied to the patterning member, so that the resistances are respectively connected sequentially. Thus, upon the application of the hold signal, the patterning member is held to generate a pattern signal and the connection of the resistances is fixed by the fused-off of the fuses.
    Type: Grant
    Filed: June 29, 1987
    Date of Patent: January 17, 1989
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Kenji Ueda