Abstract: A calculation processing apparatus is disclosed. In one example, an exclusive memory stores an exclusive area different from an address space of a processor. A data transfer unit performs transfer processing of data items between the address space and the exclusive memory. A calculation processing unit performs calculation processing between the data items stored in the exclusive memory. A command resistor group holds each command of command columns received from the processor in each resistor. A state machine manages a state of processing in the data transfer unit and the calculation processing unit. A control unit controls the command resistor group so as to hold the command and controlling the command resistor group such that the commands held by the command resistor group are fed to any of the data transfer unit and the calculation processing unit depending on the state.

Abstract: A storage system having a processor that provides a volume to be an object of an input/output (I/O) request and executes I/O in response to the I/O request includes a valid volume provided to be the object of the I/O request, and an invalid volume not being provided to be the object. A plurality of invalid volumes includes invalid volumes of a plurality of types of capacities. The processor selects, when a volume creation request is received, the invalid volume on the basis of capacity according to the volume creation request to convert the selected invalid volume into a valid volume, and provides the validated valid volume.

Abstract: A data storage and retrieval system for a computer memory including a memory slice formed of segments and adapted to contain one or more documents and a checkpoint adapted to persist the memory slice. The checkpoint includes a document vector containing a document pointer corresponding to a document. The document pointer including a segment identifier identifying a logical segment of the memory slice and an offset value defining a relative memory location of the first document within the identified segment. There are checkpoint memory blocks, each storing a copy of a corresponding segment of the memory slice. The segment identifier of the document pointer identifies a checkpoint memory block and the offset value of the document pointer defines a relative location of the document within the checkpoint memory block.

Abstract: A memory control method for a rewritable non-volatile memory module which includes a plurality of physical groups is provided according to an exemplary embodiment of the disclosure. The memory control method includes: storing first table information into a first physical group among the physical groups, wherein the first table information records management information corresponding to a first logical range; storing second table information into a second physical group among the physical groups, wherein the second table information also records the management information corresponding to the first logical range; and instructing a reading of the second table information from the second physical group to obtain the management information corresponding to the first logical range in response to that the first physical group is in a default status.

Abstract: The present invention discloses a storage device including a memory module and a memory controller. The memory controller includes a memory interface control unit, a command queue, a selecting unit, a buffer and a processing unit. The processing unit is configured to perform: generating a plurality of macro commands by combining a plurality of sequences of memory operation commands; writing the macro commands into the buffer; writing one or more than one operation parameter of the macro command corresponding to a host command into the buffer according to the host command outputted from a host; commanding the selecting unit to select the buffer as an input terminal; and commanding the buffer to output the macro command corresponding to the host command.

Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.

Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.

Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: The present invention provides persistent memory storage engine device based on log structure and a control method, including persistent memory allocators, persistent operation logs, and a volatile index structure. The control method of log structure-based storage engine includes: allocating by persistent memory allocators, new spaces to each processor for storing updated key value pairs; organizing acquired operation information into compact log entries, and adding compact log entries into persistent operation logs according to first preset rule, where first preset rule is performing batch persistency on compact log entries from the plurality of processor cores; and updating index entries in volatile index structure to point to new key value pairs. This application fully exploits opportunity to reduce persistence overhead by redesigning log structure storage format and batch persistence mode.

Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

Abstract: Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.

Abstract: A technique for managing write requests in a data storage system checks whether newly-arriving data match previously-stored data that have been recorded in a deduplication database. If a match is found, the technique compares mapping metadata for the newly-arriving data with mapping metadata for the matching data. If both sets of metadata point to the same storage location, then the newly-arriving data is a same-data write and a new write to disk is avoided.

Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.

Abstract: A data storage service obtains derivation code and data. The derivation code is executable to generate derived data from the data. The data storage service stores the derivation code and the data in a logical data container. In response to receiving a request to obtain the derived data, the data storage service uses the derivation code to regenerate the derived data from the data and transmits the derived data to fulfill the request.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: A non-volatile memory express over fabrics (NVMeoF) redundant array of independent disks (RAID) controller includes an NVMeoF RAID target module, an NVMeoF RAID implementation module, and an NVMeoF RAID initiator module. The NVMeoF RAID target module receives one or more NVMeoF commands from one or more computer hosts. The NVMeoF RAID implementation module receives the one or more NVMeoF commands from the NVMeoF RAID target module and performs RAID functionalities on the one or more NVMeoF commands. The NVMeoF RAID initiator module receives the one or more NVMeoF commands from the NVMeoF RAID implementation module and transmits the one or more NVMeoF commands to the one or more storage target devices to establish one or more virtual queue pair connections and enable direct data transfer between the one or more computer hosts and the one or more storage target devices.

Abstract: One embodiment facilitates data storage. During operation, the system receives data to be stored in a non-volatile memory of a storage device. The system determines, by a flash translation layer module of a control unit which is distinct from the storage device, a physical page address at which the data is to be stored in the non-volatile memory, wherein the flash translation layer module of the control unit determines physical page addresses for data to be stored in a plurality of storage devices. The system stores, by the flash translation layer module of the control unit, a mapping between a logical page address for the data and the physical page address. The system writes the data to the non-volatile memory at the physical page address.

Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

Abstract: Example storage systems, storage nodes, and methods provide parallel storage node processing of data functions, such as map-reduce functions. Storage nodes are configured to decode erasure encoded symbols, identify subunits of a data unit from the decoded symbols, and process the subunits in parallel using map-functions to generate intermediate contexts. A reduce-function may be used to determine a function result using the intermediate contexts.

Abstract: Embodiments for defending against speculative side-channel analysis on a computer system are disclosed. In embodiments, a processor includes a decoder, a cache, address translation circuitry, a cache controller, and a memory controller. The decoder decodes an instruction. The instruction specifies a first address associated with a data object, the first address having a first memory tag. The address translation circuitry translates the first address to a second address, the second address to identify a memory location of the data object. The comparator compares the first memory tag and a second memory tag associated with the second address. The cache controller detects a cache miss associated with the memory location. The memory controller, in response to the comparator detecting a match between the first memory tag and the second memory tag and the cache controller detecting the cache miss, loads the data object from the memory location into the cache.