Patents Examined by Richard Roseen
  • Patent number: 6011410
    Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: January 4, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Song C. Kim, Kuan-yu J. Lin
  • Patent number: 6008669
    Abstract: A monolithic integrated multiple mode circuit having an output stage, a transfer gate, a control circuit arrangement, and a well contacting region where a well potential may be applied, the multiple mode circuit adapted to be controlled into an output stage mode or an input stage mode by means of control data.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: December 28, 1999
    Assignee: STMicroelectronics GmbH
    Inventor: Wolfgang Gerner
  • Patent number: 6005413
    Abstract: A tri-state input-output (I/O) buffer which includes a core terminal, a pad terminal and an enable terminal. A pad pull-down transistor and pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. A pull-down control circuit is coupled between the core terminal and the pull-down control terminal. A pull-up control circuit is coupled between the core terminal and the pull-up control terminal. A feedback circuit is coupled between the pad terminal and the pull-up control terminal for sensing a first voltage on the pad terminal and adjusting a second voltage on the pull-up control terminal based on the sensed first voltage to reduce leakage current through the pull-up transistor when an enable signal received on the enable terminal is an inactive state.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: December 21, 1999
    Assignee: LSI Logic Corporation
    Inventor: Jonathan Schmitt
  • Patent number: 6002269
    Abstract: A bootstrap logic driver circuit operable from a low voltage power supply includes first and second bipolar transistors coupled between positive and negative voltage supplies and having a collector load comprising a first diode structure. A further transistor coupled between the voltage supplies has a collector load comprising a second diode structure. A bootstrap capacitor coupled between the diode structures stores charge when the circuit is in a first condition and is discharged when the circuit is in a second condition to provide an enhanced drive voltage for an output transistor.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: December 14, 1999
    Assignee: Northern Telecom Limited
    Inventors: Peter Dartnell, Joseph Chan
  • Patent number: 5994921
    Abstract: A sender device capable of sending digital information in the form of electrical binary signals to a receiver device. N-MOS transistors and P-MOS transistors are arranged in pairs. Each pair comprises an N-MOS transistor and a P-MOS transistor. The N-channel of an N-MOS transistor located in one pair, and the P-channel of a P-MOS transistor located in the same pair are connected in parallel, whereby a broad signalling voltage range is accomplished.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: November 30, 1999
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Mats Hedberg
  • Patent number: 5986468
    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: November 16, 1999
    Assignee: QuickLogic Corporation
    Inventors: Andrew K. Chan, John M. Birkner, Hua-Thye Chua
  • Patent number: 5986474
    Abstract: A circuit for generating a voltage for pre-charging a data line. The circuit receives as input an ON/OFF signal which is typically the data bus line equalization control signal. The circuit also receives a varying power voltage. The circuit includes a bleeder which biases the data line at a voltage differing from said varying power voltage by a constant amount when the circuit is ON. The circuit consumes substantially zero power when OFF.
    Type: Grant
    Filed: January 12, 1996
    Date of Patent: November 16, 1999
    Assignee: Mosel Vitelic, Inc.
    Inventors: Jinyong Chung, Li-Chun Li, Pochung Young
  • Patent number: 5986475
    Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: November 16, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Song C. Kim, Kuan-yu J. Lin
  • Patent number: 5977799
    Abstract: Since the logic levels on both edge sides (node n1 and node n2) of an NMOS connected to a word line are set to the same level corresponding to the logic level of the chip enable signal, even in a memory having an MOS transistor with a short gate length due to an increase of the storage capacity, a leak voltage can be prevented from taking place in the chip standby state.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: November 2, 1999
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Nobuhiro Kai, Hitoshi Kokubun
  • Patent number: 5973512
    Abstract: A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: October 26, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Alan J. Baker
  • Patent number: 5969544
    Abstract: A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: October 19, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takenobu Iwao, Nobuyuki Ikeda, Miho Yokota
  • Patent number: 5966032
    Abstract: Several low power, low voltage swing, BiCMOS circuits for used in high speed chip-to-chip communications are described. In particular a BiCMOS low voltage swing transceiver comprising a driver and a receiver with low on-chip power consumption is reported. Operating at 3.3.V, the universal transceiver can drive and receive low voltage swing signals with termination voltages ranging from 5V down to 2V, without using external reference voltages and at frequencies exceeding 1 GHz. On-chip power consumption is much lower than that of known CML/ECL type transceivers having comparable speeds.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: October 12, 1999
    Assignee: Northern Telecom Limited
    Inventors: Muhammad S. Elrabaa, Mohamed I. Elmasry, Duljit S. Malhi
  • Patent number: 5966030
    Abstract: An output driver circuit includes first and second supply terminals, first and second complementary data terminals and an output terminal. A pull-up transistor is coupled between the first supply terminal and the output terminal and has a first control terminal. A pull-down transistor is coupled between the second supply terminal and the output terminal and has a second control terminal which is coupled to the second data terminal. A voltage level shifting circuit is coupled between the first complementary data terminal and the first control terminal and is biased between the first supply terminal and a voltage-controlled node. A voltage regulator is coupled to the voltage-controlled node for regulating the node at a selected voltage.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: October 12, 1999
    Assignee: LSI Logic Corporation
    Inventors: Jonathan Schmitt, Timothy V. Statz
  • Patent number: 5963057
    Abstract: An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: October 5, 1999
    Assignee: LSI Logic Corporation
    Inventors: Jonathan Schmitt, Paul Torgerson
  • Patent number: 5959466
    Abstract: A hybrid integrate circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: September 28, 1999
    Assignee: Actel Corporation
    Inventor: John E. McGowan
  • Patent number: 5959467
    Abstract: The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: September 28, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph G. Nolan, III, John C. Holst, Donald A. Draper
  • Patent number: 5955889
    Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: September 21, 1999
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Satoshi Eto, Yoshinori Okajima
  • Patent number: 5955894
    Abstract: A method for controlling the impedance of drivers controls the output impedance of drivers by coupling the drivers to a impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manufacturing processes. Thereby shortening the signal settling time and increasing the attainable signaling frequency.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: September 21, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Sai V. Vishwanthaiah, Jonathan E. Starr, Alexander D. Taylor
  • Patent number: 5955896
    Abstract: In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: September 21, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masashi Horiguchi, Jun Etoh, Takeshi Sakata, Kan Takeuchi, Katsumi Matsuno, Masakazu Aoki
  • Patent number: RE36443
    Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: December 14, 1999
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Herman Ma, Darin L. Kincaid, David N. Larson