Patents Examined by Richard Roseen
  • Patent number: 5892370
    Abstract: A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: April 6, 1999
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Mukesh T. Lulla, Ker-Ching Liu
  • Patent number: 5889417
    Abstract: A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: March 30, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Edgardo F. Klass, Chaim Amir, David W. Poole, Alan C. Rogers
  • Patent number: 5886542
    Abstract: A quasi-complementary BICMOS circuit (46) having a clamp circuit that automatically discharges the base-collector of a pull down bipolar transistor (16) when the transistor's (16) collector voltage equalizes its base voltage. The action is immediate and does not depend on the performance of a feedback circuit to provide the timing of the arrival of the clamp signal. The clamp circuit reduces the amount of shallow saturation and quickly discharges shallow saturation after the pull down transition. The degree of shallow saturation is controllable by size selection of the clamp transistor (48). The clamp circuit also discharges the transistor's (16) base voltage to ground potential.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: March 23, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Michael D. Cooper
  • Patent number: 5886538
    Abstract: A composable memory array for a programmable logic device includes a plurality of dedicated, serially coupled memory tiles. Each memory tile includes a plurality of dual-port memory cells, each having a first port and a second port, a plurality of first bit lines coupled to the first ports and a plurality of second data lines coupled to the second ports. The first and second bit lines extend across memory tiles. Each memory tile includes a plurality of first configuration circuits which allow the first bit lines of the memory tile to be coupled to the first bit lines of the previous memory tile. Thus, any number of consecutive memory tiles can be concatenated to form a memory array using the first set of bit lines. Non-consecutive memory tiles include a plurality of second configuration circuits which allow the second bit lines of the memory tile to be coupled to the second bit lines of a previous memory tile.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: March 23, 1999
    Assignee: Xilinx, Inc.
    Inventor: Bernard J. New
  • Patent number: 5883527
    Abstract: An output circuit for a semiconductor device that offers improved reliability of data transfer over long distance as well as low consumption. In one embodiment, an output circuit according to the invention includes: an output circuit section having a pair of output terminals for outputting complementary output signals in response to an input signal received by the output circuit section, and a switch circuit connected between the pair of output terminals of the output circuit section. The output circuit section sets the pair of output terminals in a high-impedance state in response to a high-impedance setting signal received by the output circuit section. The switch circuit causes electric coupling between the pair of output terminals in response to the high-impedance setting signal.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: March 16, 1999
    Assignee: Fujitsu Limited
    Inventor: Teruhiko Saito
  • Patent number: 5883525
    Abstract: An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: March 16, 1999
    Assignee: Xilinx, Inc.
    Inventors: Danesh Tavana, Wilson K. Yee, Victor A. Holen
  • Patent number: 5880601
    Abstract: A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: March 9, 1999
    Assignees: Hitachi, Ltd., Hitachi Communication Systems, Inc.
    Inventors: Nobuaki Kanazawa, Masao Mizukami, Kunihiro Ito
  • Patent number: 5880598
    Abstract: Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: March 9, 1999
    Assignee: Xilinx, Inc.
    Inventor: Khue Duong
  • Patent number: 5877634
    Abstract: A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to-high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed.
    Type: Grant
    Filed: April 23, 1993
    Date of Patent: March 2, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Steven A. Hunley
  • Patent number: 5874835
    Abstract: A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masahiko Ishiwaki, Harufusa Kondoh, Hiromi Notani
  • Patent number: 5874838
    Abstract: An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage V.sub.cc, and the I/O cell output pad. The n-channel transistor is biased substantially continuously on its gate terminal with a pumped voltage from a charge pump, which permits it to pass voltages up to and including V.sub.cc. The p-channel transistor operates in its normal fashion, controllable via a pullup select signal applied to its gate terminal to pull the pad high. During normal operation, the n-channel transistor is always ON, thus reducing the substantial dynamic current drawn from the charge pump. The voltage appearing on the pad is fed back to a second n-channel transistor. When the voltage on the pad exceeds V.sub.cc for example, a 5 volt signal when V.sub.cc is 3.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: February 23, 1999
    Assignee: Cypress Semiconductor Corporation
    Inventor: David B. Rees
  • Patent number: 5872463
    Abstract: The output signals of the logic regions in a programmable logic integrated circuit device are programmably connectable to output bus conductors. Each such output signal can be applied to any of several of these conductors, and each conductor can receive any of several output signals. Each output bus conductor is connectable to one or more output drivers (e.g., through a programmable connector it shares with another output bus conductor). The output drivers can drive more general interconnection resources of the device. This device architecture increases logic region output signal routing flexibility and/or allows the number of output drivers to be decreased (i.e., by making more efficient use of the output drivers that are provided).
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: February 16, 1999
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 5867040
    Abstract: The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneaki Fuse, Yukihito Oowaki
  • Patent number: 5864243
    Abstract: A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: January 26, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Deng-Yuan David Chen, Waseem Ahmad
  • Patent number: 5859544
    Abstract: A programmable logic device using dynamic programmable elements to store configuration data is refreshed by periodic writing of configuration data from the source memory into the dynamic programmable elements. The invention takes advantage of smaller sized dynamic programmable elements and eliminates the need to perform tedious read/sense operation for each refresh cycle.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: January 12, 1999
    Assignee: Altera Corporation
    Inventor: Kevin Alan Norman
  • Patent number: 5859541
    Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: January 12, 1999
    Assignee: Motorola, Inc.
    Inventors: Steven Craig McMahan, Kenneth Charles Scheuer, William Burl Ledbetter, Jr., Michael Gordon Gallup, James George Gay
  • Patent number: 5859542
    Abstract: A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABS) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: January 12, 1999
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 5854561
    Abstract: A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: December 29, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazutami Arimoto, Masaki Tsukude
  • Patent number: 5852370
    Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5). A first inverter (5526) is connected between first supply voltage (3.3v) and ground and has a first inverter input (IN) and a first inverter output. A second inverter (5518) is connected between second supply voltage (5v) and ground and has a second inverter input (INT) and a second inverter output (OUT). A first feedback transistor (5520) has connections to the second supply voltage (5v), and to the second inverter input (INT) and the second inverter output (OUT). A second feedback transistor (5524) has connections to ground, and to the second inverter input (INT) and the second inverter output (OUT). First and second open-type inverters (5522, 5528) are connected to ground and each of the open-type inverters has an input and output.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: December 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Uming Ko
  • Patent number: RE36123
    Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.
    Type: Grant
    Filed: June 15, 1995
    Date of Patent: March 2, 1999
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Flavio Scarra, Maurizio Gaibotti, Giampiero Trupia