Abstract: A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In a first embodiment, a BE-SONOS sub-gate-AND array architecture is constructed multiple columns of SONONOS devices with sub-gate lines and diffusion bitlines. In a second embodiment, a BE-SONOS sub-gate-inversion-bitline-AND architecture is constructed multiple columns of SONONOS devices with sub-gate inversion bitlines and with no diffusion bitlines.

Abstract: Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

Abstract: A semiconductor integrated circuit device includes first to third memory cell units, first and second bit lines, and first and second source lines. The first to third memory cell units include memory cell transistors serially connected between selection transistors. The first bit line is commonly connected to one end of the current path of the first memory cell unit and one end of the current path of the second memory cell unit. The second bit line is connected to one end of the current path of the third memory cell unit. The first source line is connected to the other end of the current path of the first memory cell unit. The second source line is commonly connected to the other end of the current path of the second memory cell unit and the other end of the current path of the third memory cell unit.

Abstract: A circuit arrangement for the defined discharge of a capacitive load includes a first connecting terminal for connection of the load, a second connecting terminal for application of a predetermined potential, and a third connecting terminal for application of a discharge signal. The circuit arrangement further includes a first switching element, having a load path and a control connection, the load path of which is connected between the first and second connecting terminals and a second switching element, having a load path and a control connection, the load path of which is connected between the first connecting terminal and a terminal for reference potential. The first switching element is driven in a manner dependent on a switching state of the second switching element. The second switching element is driven by a drive circuit to which the discharge signal is fed and which includes a comparator arrangement.

Abstract: A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

Abstract: A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line.

Abstract: A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26, so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36, and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.

Abstract: A system and method for writing to a magnetic memory written in a thermally assisted manner, each memory point formed by a magnetic tunnel junction, and having a substantially circular cross-section of the memory which is parallel to the plane of the layers forming the tunnel junction. The tunnel junction includes at least a trapped layer with a fixed magnetisation direction, a free layer with a variable magnetisation direction with an insulating layer arranged there between. The free layer is formed from at least one soft magnetic layer and a trapped layer, with the two layers being magnetically coupled by contact. During read operations and at rest, the operating temperature of the memory is lower than the blocking temperature of the free and trapped layers, respectively.

Abstract: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.

Abstract: Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

Abstract: A functional molecular element whose functions can be controlled by an electric field based on a new principle. A Lewis base molecule (14) with positive permittivity anisotropy or a dipole moment in the major axis direction of the molecule is disposed, via a metal ion (3) that can act as a Lewis acid, in a pendant-like form on a key molecule (2) in the form of a line or film that has a conjugated system and exhibits conductivity, thereby forming a functional molecular element 1 that can realize a function where the conformation changes due to the application of an electric field. The conductive key molecule (2) and the Lewis base molecule (14) form a complex with the metal ion (3). When an electric field is applied in a direction perpendicular to the plane of the paper in FIG. 1(b), for example, the Lewis base molecule (14) performs a 90° “neck twisting” movement with the up-down direction in the drawing as the axis.

Abstract: A low voltage, high-gain current/voltage sense amplifier (ISA/VSA) circuit with improved read access time is provided herein. According to one embodiment, the ISA/VSA described herein includes a pair of current reference branches for generating a pair of reference currents in response to a pair of differential input signals supplied thereto. The differential input signals are differential voltages which are converted to differential currents by the current reference branches. In some cases, the current reference branches may be used for amplifying and mirroring the reference currents onto output nodes of the ISA/VSA. In doing so, the current reference branches may increase the amplification and improve the performance of the sense amp circuit, even under extreme mismatch conditions. In addition, positive feedback may be used within the ISA/VSA design to further increase the amplification and speed of the sense operation.

Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Abstract: An embodiment of the present invention relates to a repair circuit of a semiconductor memory device. The repair circuit includes an address counter that sequentially generates a first column address signal and a second column address signal in response to a write enable signal or a read enable signal, a repair controller that generates a repair column address signal earlier than the second column address signal in response to the first column address signal, an address latch enable signal, a command enable signal, and a write enable signal, and a repair scramble unit that selects a repair cell in response to a repair I/O control signal and the repair column address signal. If an address on which a repair operation must be performed occurs, the repair controller directly receives the write enable signal or the read enable signal and activates the repair controller earlier than a general cell using a previous address, thereby offsetting an operating time consumed in the repair controller.

Abstract: A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

Abstract: A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell, and third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line or signal line.

Abstract: A sector erase method for use in a non-volatile memory, such as a FLASH memory, including a plurality of memory cells in rows and columns, the memory cells being divided into a plurality of sectors. The sector erase method includes erasing the memory cells of a first sector by applying successive erase pulses that increase in voltage magnitude or pulse width, until erasure of the first sector is verified. Erase condition information corresponding to the first sector, is recorded, this information including a number of times successive erase pulses are needed to be applied in order to erase the memory cells of the first sector. Memory cells of a next sector are erased by applying a first erase pulse having a voltage magnitude or pulse width determined from the recorded erase condition information. The first erase pulse may be incremented if the first erase pulse fails to erase that next sector.

Abstract: The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific ROM(3). Then, the selected data are compared with expected values to thereby perform testing thereof. Therefore, the contents of the ROM(3) are also tested within the time required to test each of the ROM(1) and ROM(2), thus making it possible to shorten a test time.

Abstract: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.