Abstract: Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the circuit. Upon successful selection and clean up of system clock, the reset is removed.

Abstract: A tagging and arbitration mechanism in an input/output node of a computer system. A mechanism for tagging commands in an input/output node of a computer system includes a tag circuit configured to receive a plurality of control commands. The tag circuit may also be configured to generate a tag value for each of the control commands. The tagging mechanism may also include a buffer circuit which is coupled to the tag circuit. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. Further the tagging mechanism may include an arbitration circuit that is coupled to the buffer circuit and is configured to arbitrate between the plurality of buffers depending upon the tag value for each of the control commands.

Abstract: The present invention captures streaming data and avoids continual retrieval. The invention only looks at data once, has a time dependency built into it, and data that is not consumed or relevant is discarded. The invention includes an engine processor that processes data according to stored information; stored rules that define engine operation, an input events module for receiving events which provides a plurality of events. Events are processed according to stored rules for generating a series of valid results when input events match the rules. Rule states that have been matched to an input event but have not produced a valid result are stored in state storage. The state of a rule as stored enables the engine to provide a valid result output upon a future reception of an input event necessary to complete the rule. Transaction log module monitors the operation of the engine for specified time period.

Abstract: A communication system having a controlled device (105), for which an abstract representation (AR) (107) is provided as interface on a controlling device (103). When the quality of the connection between the controlling device (103) and the controlled device (105) drops below a predetermined level, or if some similar criterion is met, the system selects a second controlling device (104) which is better suited for controlling the controlled device (105) and generates a migration event to indicate this. The first controlling device (103) transfers control over the controlled device (106) to the second controlling device when it receives said migration event. This can be done by uploading the AR (107) to the second controlling device (105), possibly supplemented with the current state of the AR (107) to perform a fully transparent transfer.

Abstract: A method and system for managing I/O resources for communications between a host and a target device through at least one adapter, involves setting a local resource associated with each adapter. If a target device cannot accept an I/O request, the local resource associated with each adapter is set to the number of I/O resources currently used by each adapter associated therewith. The host is configured to issue no more than the local resource number of I/O requests to any individual adapter. The local resources may be periodically rebalanced to account for changes in system needs.

Abstract: System and method for device support. The system may comprise a processor, a memory, a device controller and a basic input-output system (BIOS). The memory may be mapped according to a predetermined specification, such as the Advanced Configuration and Power Interface (ACPI) specification. A device support component in the BIOS uses a portion of a defined region of the memory, such as the non-volatile sleeping (NVS) memory region, to maintain device data for a device. A method involves providing the software component in the BIOS. The software component maps the memory, reserving a portion of the defined region of the memory to maintain a plurality of device data regarding the device controller, and provides support for at least one device utilizing the portion of the defined region of the memory. The system and method may be used with Universal Serial Bus (USB) devices and controllers, as well as with secondary graphics adapters.

Abstract: An apparatus is provided with a first and a second first in, first out storage structure (FIFO) that are correspondingly associated with a first and a second resource. The apparatus is further provided with first and second control logic correspondingly coupled to the first and the second FIFO to write a first and a second control value into a first and a second current write storage location of the first and the second FIFO respectively when the first resource is assigned with a first task. The first and second control logic further write the second and the first control value into a third and a fourth current write storage location of the first and the second FIFO respectively when the second resource is assigned with a second task. Together, the elements enable the resources to cooperatively generate results for the sink process.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: The portable CD player and burner is provided for integrating a CD-ROM player and a video/acoustic player used respectively on two different systems including a computer and a video/acoustic household electric appliance at the terminal of a device. The portable CD player and burner mainly is comprised of a housing, a CD reading/writing unit, an operating unit, a main board, a multiplexer, a CPU, a memory unit, a signal converting unit and at least an output/input unit. When a CD is placed in, signals can be transmitted to the systems of the computer or the video/acoustic household electric appliance, or the data of the computer can be transmitted to the CD reading/writing unit by using the above stated elements for outputting and inputting respectively.

Abstract: A device (e.g., a secondary cache device) manages descriptors which correspond to storage locations (e.g., cache blocks). The device includes memory and a control circuit coupled to the memory. The control circuit is configured to arrange the descriptors, which correspond to the storage locations, into multiple queues within the memory based on storage location access frequencies. The control circuit is further configured to determine whether an expiration timer for the particular descriptor has expired in response to a particular descriptor reaching a head of a particular queue. The control circuit is further configured to move the particular descriptor from the head of the particular queue to a different part of the multiple queues, wherein the different part is identified based on access frequency when the expiration timer for the particular descriptor has not expired, and not based on access frequency when the expiration timer for the particular descriptor has expired.

Abstract: A system and method are provided in a media access controller and in a physical layer device for communicating between the media access controller to a number of physical layer devices. In one embodiment, the system in the media access controller comprises a common bus port for electrical coupling to a common bus that is electrically coupled to the physical layer devices, the common bus port including a parallel data port and an enable port. The system also includes a logical circuit to transmit a data block to a respective one of the physical layer devices via the parallel data port. The logical circuit specifically proceeds the transmission of the data block with the transmission of an address block that indicates the particular physical layer device to which the data block is to be transmitted. In addition, the system in each of the physical layer devices facilitates receiving data from the media access controller.

Abstract: An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

Abstract: An adapter having a slot, a connector, and a passive router that routes signals from a smart card inserted in the slot to the connector, is disclosed.

Abstract: The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.

Abstract: A patient encounter electronic medical record system, method, and computer product includes pre-populated, diagnosis specific templates, selective, specialty-specific master databases, and anatomic specific databases and templates to achieve comprehensive, accurate and compliant medical documentation that captures patient data concurrently with the clinical patient encounter session. The system is enabled for a distributed computing environment including graphical user interfaces and voice, text, and digital image and x-ray input.

Abstract: A storage area network (SAN) fibre channel arbitrated loop (FCAL) multiple system, multiple resource, storage enclosure and a method are provided for performing enclosure maintenance concurrent with device operations. The storage enclosure includes a plurality of storage resources or storage devices, a plurality of IO adapters (IOAs) coupled to the storage area network and a pair of enclosure services node cards. Each enclosure services node card includes loop connections for the plurality of storage resources. Each enclosure services node card includes a respective global bus connection and a loop connection to each of the plurality of IOAs. Each enclosure services node card is used concurrently by the multiple systems to manage the plurality of storage resources. In the method for performing enclosure maintenance concurrent with device operations, identical maintenance procedures are implemented for the enclosure services node cards and the storage devices.

Abstract: Apparatus and method for controlling a molding machine includes structure and function for a human machine interface control panel having: (i) a flat panel display screen; (ii) a pointing device; (iii) a plurality of pushbuttons overlaid with or without icons; (iv) a housing containing the above and the associated electronics; (v) structure to uniquely identify each users preferred configuration; (vi) structure to connect to a remote controller for both digital information and video signal communication; (vii) a connection for receiving external power to drive the panel's electronics and display; and (viii) software running in the remote controller to provide all the operating functions of the human machine interface.

Abstract: An information processing apparatus performs predetermined processing by executing a computer program. A program memory stores two boot addresses #1 and #2, each of which serves as an address from which a basic program including a boot program for performing a booting operation is stored. In installing a basic program, the boot addresses #1 and #2 are alternately selected to store the basic program. In starting an apparatus, an error of the computer program stored in the program memory is detected, and upon detection, one of the boot addresses #1 and #2 is selected, and the basic program stored from the selected address is executed. The version compatibilities of a basic program or an application program are described in the basic program or the application program. Upon upgrading the version of the application program, it is determined whether the version of the application program is compatible with the version of the basic program, and vice versa.

Abstract: A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.

Abstract: An apparatus and method for efficiently performing data transfer operations in an electronic system preferably includes a plurality of buffers that may store data and commands during execution of data transfer operations. Initially, at least a portion of a plurality of commands defining data transfer operations between a memory and peripheral devices may be temporarily stored in a command buffer associated with a processor interface. The processor interface may then issue commands directly to a memory interface, peripheral devices, and peripheral interfaces within the electronic system. Commands received by the memory interface may be temporarily stored in a command buffer associated with the memory interface. When a memory associated with the memory interface is ready, the memory interface may access the memory, and transfer data to or from one or more buffers associated with a peripheral device.