Abstract: Byte-swapping in a buffer memory system utilizes a byte-swapping register to avoid wasteful unused buffer memory spaces that may result from a data transfer of partial word data, i.e., bytes of data less than the number of bytes in a word, to the buffer memory. When a data transfer request, e.g., a write request, requires a transfer of a partial word, the partial request is written to a word in the buffer memory, and is also stored in the byte-swapping register. In a subsequent data transfer request, the partial word stored in the byte-swapping register is combined and concatenated with sufficient bytes of data of the subsequent data transfer request to produce a complete word. The complete word is written in the word in the buffer memory, replacing the previously stored partial word, and thus fills the previously unused buffer memory space.

Abstract: A programmable controller (PLC) facilitates modifications to programs running thereon, readily accommodates addition and removal of intelligent modules contained therein, and offers good maintenanceability. For modifying programs in a conventional PLC which incorporates intelligent modules, programs in each of the intelligent modules must be modified since programs are individually inputted to the respective intelligent modules, thus giving rise to a problem in that an increased amount of works are required. In the PLC of the present invention, a processing unit of an intelligent module is configured equivalent to a processing unit of a CPU module, and registers and memories of respective intelligent modules are allocated in a memory map of the CPU module to build a hardware configuration which allows the processing unit of the CPU module to read and write the registers and memories of the respective intelligent modules, so that the intelligent modules can be controlled in a manner similar to the CPU module.

Abstract: In parallel-serial architecture based networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data links so that data transmission occurs at the same time in the receive path of the I/O “processor.” The processor can be an I/O device for a host channel adapter, a target channel adapter, or an interconnect switch in an InfiniBand-type network.

Abstract: There is provided an information processing apparatus having a setting unit for setting an instruction for an inquiry of the capacity of a memory on a data destination side, and a transfer unit for transferring the instruction set by the setting unit to an external apparatus. There is also provided an output apparatus having a memory for storing data received from an external apparatus, and an output unit responsive to a reception of an instruction of an inquiry of the capacity of the memory from the external apparatus, for outputting information of the capacity of the memory to the external apparatus. There is also provided an output apparatus having a plurality of motors driven for an output process or a storage process, and an inhibit unit for inhibiting, when at least one of plurality of motors is driven, the other motors to be driven.

Abstract: Disclosed is a method and computer program device for dynamically managing the assignment of alias addresses to base addresses referencing an input/output (I/O) device, such as a direct access storage device (DASD). Two distinct methods are disclosed. In one method, alias addresses are assigned based on the performance of the I/O devices. In this method, alias addresses are assigned to highly utilized devices, as indicated by device performance data, in order to maximize the efficient utilization of I/O device resources. In a second method, workload management principles are utilized to assign alias addresses. In this method, a correlation is made between each I/O device and the service classes utilizing each device. As in the first method, performance data is generated for each I/O device. Alias addresses are assigned to I/O devices experiencing queue delays as indicated by their performance data, if the device is associated with a service class that has failed to meet one or more processing goals.

Abstract: An information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool. The information processing system includes a ROM for storing an unlocking program and a user program; a CPU for executing said unlocking program and said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit when said unlocking program has been executed.

Abstract: A system for transmitting electrical signals between a computer and peripherals along a twisted pair cable. The system includes a computer interface, a peripheral interface and a twisted pair cable in communication between the computer interface and the peripheral interface. Video and audio signals from the computer are transmitted via the twisted pair cable to the peripherals. Peripheral signals can also be communicated between the computer and peripherals via the twisted pair cable.

Abstract: A method and system for providing an exact image transfer and root panel list within the panel subunit graphical user interface mechanism of networked electronic devices. The exact image transfer mechanism allows a target device to send a networked controller device a bitmap image of the exact display required of the target device. By transferring an exact bitmap of what is to be displayed, the target device can guarantee that the display rendered by the controller will not be modified or altered. This is useful in cases where the display represents an electronic program guide (EPG) or other suitable display that should be displayed with a predetermined arrangement and should not be altered by the controller. This is also useful in cases where the controller does not have a robust processing capability and therefore merely displays the exact bitmap sent by the target. Focus navigation is communicated from the controller to the target which then can alter the bitmap to illustrate an updated focus.

Abstract: A reporting system capable of reporting the end of a scanning session to a user through existing computer peripheral devices is proposed. By reporting at the end of a scanning session, the user can proceed with subsequent scanning operations with no delay. Hence, idle time of the scanner is greatly reduced.

Abstract: A keyboard system includes keyboard having an internal circuit therein, at least one I/O device, and a transceiver module. The transceiver module on the main body of the keyboard receives signals from I/O devices and transmits audio signals from at least one external device connected to the keyboard system. The keyboard further includes a plurality of pointers indicative of which I/O device is connected to the keyboard.

Abstract: A bus monitor section 8 calculates bus-occupancy rate for each of the DMA control sections 1 to 3 connected to a bus 5 in accordance with bus-use permission signals ack1 to ack3, respectively. Furthermore, a bus-use reconcilement section 6 changes manners of bus-use reconcilement control when the sum of a plurality of bus-occupancy rate exceeds “50”, a predetermined threshold. Thereby, this method avoids occurrences such that a specific device occupies the bus 5 or vice versa, a specific device cannot get access to the bus 5.

Abstract: Method of passing inbound messages to an I/O processor's local memory. A message is received in a messaging unit within the I/O processor. The messaging unit is read to fetch the message. A free local message frame address is retrieved from the messaging unit. A direct memory access unit coupled to the messaging unit is set up. The message is then copied into the I/O processor's local memory.

Abstract: A two-dimensional hardware control block execution queue facilitates multiple command delivery to a single target device over an I/O bus, such as a SCSI bus. The two-dimensional hardware control block execution queue includes a plurality of target queues where each target queue includes at least one hardware control block. Each of target queues is a queue of hardware command blocks, e.g., SCSI control blocks (SCBs) for a specific target device on the I/O bus. There is only one target queue for each target device. One head hardware control block, and only one head hardware control block of each target queue, is included in a common queue. When a selection is made by a host adapter for a target device based upon a hardware control block addressed by a head pointer to the common queue, all hardware control blocks in the target queue within the two-dimensional hardware control block queue, which are accepted by the target device, are transferred to the target device.

Abstract: According to the present invention, a device and method accomplish in-line serial programming of a default configuration into a configurable device for connection to a message-based network. The configurable device includes an input/output unit, an electrically programmable read only memory (EPROM), programming logic and a protocol engine for exchanging messages with a message-based bus based on the default configuration. The input/output unit includes pins and logic for configuring a portion of the pins to operate in both a normal mode and as a clock pin, a data pin and a program pin in a programming mode. The electrically programmable read only memory (EPROM) stores a default configuration for the configurable device. The programming logic is coupled to the input/output unit. It receives signals from the data, clock and program pins and determines data and commands based on the signals.

Abstract: Systems and methods for providing accelerated data storage and retrieval utilizing lossless and/or lossy data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly or lossy compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly or lossy decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device.

Abstract: An apparatus and method for fault resilient booting of a multi-processor system. The apparatus attempts a cold reset of the system, during which each processor performs a built-in self test. The apparatus selects a boot strap processor to perform a warm reset, during which any failed processors are tristated using a flush command. If no boot strap processor is available, the apparatus performs the warm reset and tristates any failed processor including the processor predesignated to be the boot strap processor, and then repeats the attempt to establish the boot strap processor.

Abstract: Method and system for providing data communication through a port of a system, the port having at least two operating modes, each of which corresponding to a different data rate. Communication with the system is enabled by operating the port in one of the operating modes. The system is switched to operate in another operating mode and the communication with the system is continued in the another operating mode, whenever a predetermined mode switching code is received through the port.

Abstract: A method and system for performing direct memory access (DMA) transfers using operating system allocated I/O buffers provides a mechanism for device to device transfers without utilizing global system memory. Memory is allocated on a local bus to which both devices have a requested degree of affinity and transfers are performed to and from this memory. Operating system routines provide for selection of global system memory or local memory based on whether there is local memory available to which both devices have a requested degree of affinity. The memory can be deallocated after each transfer and reallocated for each subsequent transfer.

Abstract: An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.

Abstract: A method and apparatus for interfacing ADSL modems to a codec, wherein a total of four frame buffers are used for receiving and transmitting data from and to the codec. The present invention also enables interoperability between ADSL modems that use 128 tones and those that use 256 tones.