Abstract: An information processor including a plurality of processors interconnected by communication means, each processor having a memory storing a program and data, an instruction interpretation section for interpreting instructions in the program, and an instruction execution section for executing the result of interpretation. Each processor referring to the address of source data or destination data indicated by an operand of a data transfer instruction, and determining which of the plurality of processors the source data or destination data pertain.

Abstract: A method and apparatus for instantaneously and discontinuously moving the cursor in a computer system to any one of a plurality of user-selected screen positions is disclosed. In many known computer systems, a cursor control device known as a mouse is used to move and manipulate the position of the display's cursor. In a first preferred embodiment of the present invention, X- and Y-axis position sensing means are incorporated into the mouse's known electronics. A program correlates a plurality of X- and Y-axis mouse positions with a plurality of cursor positions on the display. When the computer user moves the cursor control device into any one of these programmed positions, the cursor on the display automatically moves to the predetermined position.

Abstract: A three-dimensional computer image variable perspective display system provides for the real-time perspective control of a three-dimensional computer generated image controlled by the head movements of a computer operator viewing the image. The system includes an ultrasonic transmitter module worn on the head of the computer operator, a set of ultrasonic receivers mounted on or near the computer display monitor, and a computer interface unit. The ultrasonic transmitter transmits sound waves towards the display monitor which are detected by the ultrasonic receivers and processed by the computer interface unit. The computer interface unit calculates the elapsed times between the transmission and reception of the sound waves and converts this information into digital data words. The quantative magnitude of these data words represent in direct proportion, the instantaneous distance between the ultrasonic transmitter and the ultrasonic receivers.

Abstract: A video compression system comprises a pre-processing section, an encoder, and a post-processing section. The pre-processing section employs a median decimation filter which combines median filtering and decimation process. The preprocessing section also employs adaptive temporal filtering and content adaptive noise reduction filtering to provide images with proper smoothness and sharpness to match the encoder characteristics. The encoder employs a two pass look-ahead allocation rate buffer control scheme where the numbers of bits allocated and subsequently generated for each block may differ. In the first pass, the means square error for each block is estimated to determine the number of bits assigned to each block in a frame, In the second pass, the degree of compression is controlled as a function of the total number of bits generated for all the preceding blocks and the sum of the bits allocated to such preceding blocks.

Abstract: An I/O command issuing control system is applied to a data processing system including a processor module provided with a CPU and an adaptor module which is connected to the processor module via a system bus. The adaptor module controls an I/O device on the basis of an I/O command from the processor module. The CPU carries out separate processes after issuing an I/O command and the adaptor module returns a result of a process, which result is based on the I/O command from the processor module. An interrupt request is made, when a process in the adaptor module is unsuccessful, to the CPU inside the processor module in order to provide the CPU with the process result of the adaptor module.

Abstract: An image processing apparatus includes a window setting device for setting a portion of a written region of an image composed of dots in an orthogonal matrix as a window, and for moving the set portion within the written region. A first edge detecting device serves to detect differences between image data of a given dot in the window set by the window setting device and image data of dots neighboring the given dot, and serves to detect directions of the detected differences. A second edge detecting device serves to detect edges between neighboring dots other than the given dot, the detected edges relating to image data differences and image data difference directions respectively equal to the image data differences and the image data difference directions detected by the first edge detecting device.

Abstract: An embodiment of the present invention is a site controller that comprises a microcomputer with a RAM for main memory and an EPROM for program memory, an interface for accepting RS-485 data and voice communication on respective differential wire pairs from a daisy chain of student response keypad terminals, a public telephone data access arrangement with hybrid for sending and receiving voice over a dial-up line, a universal asynchronous receiver-transmitter for data communication by modem with a remote host site via an X.25 PAD and an audio processor for half-duplex communication between an instructor and a student that has voltage controlled amplifiers and side chain devices that reduce audio amplifier gain during periods of silence in order to eliminate feedback howl and adjustable delay and threshold devices for gating the respective channels through in the half-duplex mode.

Abstract: A fully programmable, graphics microprocessor is embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment, a video game system is described including a host video game system and a pluggable video game cartridge housing the graphics microprocessor. The game cartridge also includes a read-only program memory (ROM) and a random-access memory (RAM). The graphics coprocessor operates in conjunction with a three bus architecture embodied on the game cartridge. The graphics processor using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM.

Abstract: A method for parallel data transmission in a system having (i) a modem, (ii) one or more modem status terminals which detect modem status information and are connected to the modem, (iii) one or more modem control terminals which transmit modem control signals and are connected to the modem, and (iv) one or more serial signal output terminals which receive line control signals and are connected to the modem. Data signals are output via the one or more modem control terminals. Signal logic levels of these output data signals are controlled in accordance with the modem control signals. Data signals are also output via the one or more serial signal output terminals. The signal logic levels of these later output data signals are controlled in accordance with the line control signals. Data signals are input via one or more modem status terminals. The signal logic levels of the input data signals are perceived in accordance with the modem status information.

Abstract: Media composer for editing source material. The media composer includes apparatus for receiving digitizing, storing and editing video and audio source material. Computing apparatus manipulates the stored source material and output apparatus communicates with the computing apparatus to display the manipulated material and control information. The computing apparatus includes JPEG compression techniques and is programmed to provide enhanced editing features.

Abstract: The inventive method reduces the quantity of the actual number of pixels to be printed to attain a given resolution, on average, by half, with each two or pair of adjacent pixels of the original print information being sequentially processed to form a print pixel and a socalled white or unprinted pixel. The arrangement of print pixels and white pixels is effected so as to print a checkerboard pattern. The ink droplets accordingly have the smallest possible substrate or print media contact area so that adjacent ink droplets which are not yet dry are effectively prevented from running together and thereby degrading the resulting image.

Abstract: In a microcomputer according to the present invention, output pulse levels are stored in bit coles corresponding to respective addresses of a memory circuit which are outputted from a timer circuit which uses a clock as a count source, and each bit output of the memory circuit is latched in synchronism with the clock and outputted to a port output circuit, so as to obtain a plurality of desired phase pulses having different cycles.

Abstract: Lazy Write disk cache systems are often utilized in disk cache designs. In such systems, data to be written to the disk storage system is temporarily placed in cache memory for a preselected period of time until an actual update of the disk occurs. By deferring disk write operations input/output performance efficiency is enhanced. However, in sector-based disk storage systems in which data may only be read from or written to a disk in predetermined fixed amounts an attempted update of data often requires a read of data from the disk storage system to ensure that existing data is not written over during an update. The method and system of the present invention avoids this problem by maintaining a status table for each block of cache memory which includes an identification of each byte within each block of cache memory which will be updated.

Abstract: In accordance with the present invention, an improved printing machine for concurrently processing first and second sets of image data is provided. The printing machine preferably comprises a video processor, capable of processing the first set of image data, a system memory, adapted to store the second set of image data, and a bus for transmitting image data, addresses and control data thereacross. Both of the video processor and the system memory are coupled with the bus. Additionally, an apparatus for transferring the second set of image data between the input/output device and the system memory substantially concurrent with the first set of image data being processed in the video processor is provided. The transferring apparatus preferably transfers the second set of image data in response to receiving a signal from the input/output device.

Abstract: A distributed artificial intelligence data acquisition and equipment control system forms a local area network (LAN) over the AC power lines of a vessel for communicating shipboard engineering casualty and damage control information. Each node in the LAN includes a power line carrier current (PLCC) transceiver, a slave processing unit for interfacing with local sensors or equipment and a master processing unit for controlling the formation, transmission and reception of offset-quadrature-phase-shift-keyed (OQPSK) LAN messages. Nodes in the LAN are strategically positioned at various locations throughout the ship and are configured to function either as a Terminal Unit or as a Data & Control Unit. Terminal Units are equipped with a touch screen display and an intelligent controller that provides a user-friendly interactive operator interface through a series of display screen prompts and includes a data base of ship casualty and damage control information stored in a local non-volatile random access memory.

Abstract: An information processing apparatus such as a personal computer or a word processor is disclosed. A main unit includes at least processing means for processing input data, and main unit memory means connected to the processing means. A display device is attachable to and detachable from the main unit case and includes at least display device memory means for storing data of the main unit supplied through a connector to be connected to a main unit connector when attached, display means for displaying the stored content, control means for controlling the display and power supply means for supplying powers to the display device memory means, the display device and the control means when detached.

Abstract: An input/output interface for converting between data patterns in bit-parallel and word-serial format and data patterns in word-parallel and bit-serial format. In combination with a parallel processor, the inputting and outputting rates of the data are to be increased. To this end, a three dimensionally organized memory with a three-dimensional addressing is connected to the input and/or to the output of the parallel processor. Each address is composed of three components, of which a first component represents the significance of a bit, the second component represents the running number of the word in a limited sequence of words, and the third component represents the running number of the sequence, to which the word belongs. A switching network for the control of the memory is associated with the memory. The memory is arranged to buffer an incoming data stream of bit-parallel and word-serial format.

Abstract: A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a computer system that employs a number of such peripheral circuits that are selectively rendered operable by the CPU, one at a time. The peripherals each include an interface that receives an initial data word from the CPU that identifies the peripheral circuit with which data is to be transferred by the CPU. Rather than all such peripherals in a computer system being powered-up in order to have their processors determine individually under software control whether they have been identified by the CPU, only a small hardwired interface circuit is so enabled. Once this interface circuit determines that the CPU desires to conduct data transfer with it, the main portion of the circuit, including its processor, is then powered-up.

Abstract: An arbitration method is disclosed which insured that both write data and ordered read responses achieve fair access to a data bus in a computer system which comprises demultiplexd commands and data buses and a plurality of processors.

Abstract: In a digital computer with multiprocessor arrangement, each processor is a highly integrated computer chip on a semiconductor basis connected to the other processors in the arrangement, which are of same design, via highly meshed management system composed of meshes and nodes for transmitting digital signals. Peripheral devices such as keyboards, memories, monitors, image sensors, speech analysis units, speech synthesis units as well as transmitters are connected to the computer. According to the invention, the management system is a beam waveguide network. Each node is associated with a processor to which it is coupled via an optical emitter and an optical receiver. The new types of chip interconnection which result and hence the high packing density of the chips and large number of cross-connections obtained are particularly advantageous. The computer network has a high functional density and the computer and peripherals are unaffected by electromagnetic influences.