Patents Examined by Robert P. Limanek
  • Patent number: 6051488
    Abstract: Methods of forming semiconductor switching devices having trench-gate electrodes include the steps of implanting base region dopants of second conductivity type into a semiconductor substrate to define a preliminary base region therein. A step is then performed to form a trench having sidewalls which extend through the preliminary base region. A sacrificial insulating layer is then formed on the sidewalls of the trench while the implanted base region dopants are simultaneously diffused into the region of first conductivity type. The sacrificial insulating layer is then removed. Next, a gate electrode insulating layer is formed on the sidewalls and on a bottom of the trench. A gate electrode is then formed on the gate electrode insulating layer. Dopants of first conductivity type are then implanted into the semiconductor substrate to define a preliminary source region, which forms a P-N junction with the implanted base region dopants, and into the gate electrode to improve the conductivity thereof.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: April 18, 2000
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Tea-Sun Lee, Sung-Kyu Song
  • Patent number: 5714802
    Abstract: A highly dense electronic module for installation into a computer or other electronic device comprises at least one wafer or wafer section and means for connection with the electronic device. With an embodiment comprising plural wafer sections, the wafer sections are mechanically joined and electrically coupled.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: February 3, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Eugene H. Cloud, Alan G. Wood
  • Patent number: 5671061
    Abstract: The assessment of the effects of yarn faults is carried out by simulating the fabric image. In a first step, the yarn is examined by a measuring member for parameters associated with the volume and/or the surface. In a second step, these parameters are converted into grey values or color values, and these values are assigned to image spots. Finally, the image spots are reproduced on a video display unit and/or a printer. An image is generated thereby, representing a simulation of a woven or knitted fabric produced from the examined yarn.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: September 23, 1997
    Assignee: Zellweger Luwa AG
    Inventor: Robert Hoeller
  • Patent number: 5648666
    Abstract: This invention discloses a heterojunction bipolar transistor (HBT) which includes a relatively thin intrinsic collector region and a relatively thick extrinsic collector region such that collector-base capacitance is reduced and electron transit time is maintained. The fabrication of the HBT includes loading a semi-insulating substrate into an molecular beam epitaxy machine, and growing a sub-collector contact layer, a bottom collector layer and a top collector layer on the substrate. Next, the substrate is removed from the molecular beam epitaxy machine and the top collector layer is etched by a photolithographic process to produce separate intrinsic and extrinsic collector regions. Then, the substrate is again loaded into the molecular beam epitaxy machine so that the base and emitter layers can be grown. And finally, the emitter layer is etched to form an emitter mesa only over the intrinsic semiconductor region.
    Type: Grant
    Filed: April 13, 1994
    Date of Patent: July 15, 1997
    Assignee: TRW Inc.
    Inventors: Liem Thanh Tran, Dwight Christopher Streit, Aaron Kenji Oki
  • Patent number: 5646879
    Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: July 8, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Steven T. Harshfield
  • Patent number: 5646430
    Abstract: In one embodiment, a non-volatile memory structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region. 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: July 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Cetin Kaya, David Liu
  • Patent number: 5623243
    Abstract: A semiconductor device having a roughed surface, which is useful for a capacitor electrode is disclosed. The device is featured by depositing a polycrystalline silicon layer in such a manner that polycrystalline grains having a hemispherical like shape or a mushroom like shape are caused at the surface of the polycrystalline silicon layer. A dielectric is formed on the polycrystalline layer having an uneven surface. A conductive layer is formed on the dielectric layer. The semiconductor device thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area from the hemispherical like shaped or mushroom like shaped polycrystalline grains.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: April 22, 1997
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi
  • Patent number: 5619072
    Abstract: Increased densification in a semiconductor chip is provided by a negative enclosure of a conductive via utilizing an etch stop insulating material.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: April 8, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sunil Mehta
  • Patent number: 5610421
    Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: March 11, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Claudio Contiero, Tiziana Cavioni, Stefano Manzini
  • Patent number: 5600161
    Abstract: The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: February 4, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Angus C. Fox, III
  • Patent number: 5598037
    Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: January 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shin Kikuchi, Mamoru Miyawaki, Genzo Monma, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda, Tetsunobu Kohchi
  • Patent number: 5596213
    Abstract: A Flash EPROM cell having buried source-side injection allows for low voltage programming from the source side. A cell having the inventive structure can be programmed at 4.0 V or less. The inventive cell comprises a source area which is at a lower plane than the drain region, and a program charge is transferred to the floating gate through the source-side injector. Instead of using a self-aligned high-energy n-type dopant implant at the source side to form the source side injector as used with previous cells, which can be difficult to control, etching the substrate before impurity doping allows for the controllable formation of a sharp point of doped silicon, and allows for improved programming at a lower voltage.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: January 21, 1997
    Assignee: Micron technology, Inc.
    Inventor: Roger Lee
  • Patent number: 5591998
    Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: January 7, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
  • Patent number: 5592004
    Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: January 7, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Muneo Tamura, Takeshi Yamauchi, Katuhide Niwa, Takeshi Fukazawa, Akira Kuroyanagi, Tooru Yamaoka
  • Patent number: 5589713
    Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 .mu.m in size and having an aspect ratio greater than 1.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: December 31, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-in Lee, Chang-soo Park
  • Patent number: 5589699
    Abstract: The structure of the invention employs a lamination type memory cell and a lamination type select transistor having a floating gate. Since no contact holes are formed in a first polysilicon film of a high resistance, it is not necessary to form a contact hole in the gate wire of the select transistor between a cell array. A floating gate is beforehand charged with electricity so that the select transistor cab have a positive threshold value. Alternatively, an impurity is introduced into the channel region of the select transistor so that the neutral threshold voltage of the transistor after radiation of ultraviolet rays can have a positive value.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: December 31, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Araki
  • Patent number: 5587606
    Abstract: A lead frame includes a die pad on which a semiconductor chip is mounted, a plurality of leads each having an end which faces the die pad, and tie bars connecting the leads, wherein each of the tie bars is formed so as to project from a surface of each of the leads by an amount sufficient to break a boundary between a tie bar and a lead when the tie bar is pushed back so that the tie bar and lead is separated. The method for producing a semiconductor device using the above lead frame includes steps of clamping by molding dies the lead frame having the semiconductor chip mounted on the die pad so that the tie bar is pushed back and cut off and encapsulating the semiconductor chip by resin so that a package made of the resin is formed, and releasing the lead frame from clamping by the molding dies and removing the tie bar pushed back by the clamping from the lead frame.
    Type: Grant
    Filed: February 16, 1995
    Date of Patent: December 24, 1996
    Assignee: Fujitsu Miyagi Electronics Ltd.
    Inventor: Takashi Sekiba
  • Patent number: 5585657
    Abstract: A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: December 17, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, Roy C. Jones, III, Oh-Kyong Kwon, Michael C. Smayling, Satwinder Malhi, Wai T. Ng
  • Patent number: 5583358
    Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: December 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
  • Patent number: 5581107
    Abstract: An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: December 3, 1996
    Assignee: Fujitsu Limited
    Inventors: Shouichi Kawamura, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano