Patents Examined by Robert P. Limanek
  • Patent number: 5569954
    Abstract: A semiconductor epitaxial substrate, characterized in that a crystal is formed by epitaxial growth on a gallium arsenide single crystal substrate whose crystallographic plane azimuth is slanted from that of one of {100} planes at an angle of not more than 1.degree., that at least part of the epitaxial crystal is an In.sub.x Ga.sub.(1-x) As crystal (wherein 0<x<1), and that the epitaxial growth is carried out by chemical vapor deposition. Since the In.sub.x Ga.sub.(1-x) As layer has reduced microscopic unevenness and reduced variation in thickness, the epitaxial substrate of the present invention can be used as a channel layer of a field effect transistor or as an active layer of a semiconductor laser to endow these devices with excellent characteristics.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: October 29, 1996
    Assignee: Sumitomo Chemical Company Limited
    Inventors: Masahiko Hata, Noboru Fukuhara, Hiroaki Takata, Katsumi Inui
  • Patent number: 5569953
    Abstract: A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the molecules of the organic compound to release the group V element and oxygen.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: October 29, 1996
    Assignee: Fujitsu Limited
    Inventors: Toshihide Kikkawa, Tatsuya Ohori
  • Patent number: 5569945
    Abstract: Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patterning the first polysilicon layer and the dielectric layer by masking and etching to form a stepped electrode structure partially upon the sacrificial structure and partially upon the other exposed surfaces of the device, applying ion implantation into the substrate outside of the area covered by the stepped electrode structure, removing the sacrificial laver from the surface of the substrate and from beneath the stepped electrode structure leaving an overhanging surface of the stepped electrode structure, forming a second layer of dielectric material on the exposed surfaces of the stepped electrode structure and the substrate, and forming a second polysilicon layer over and under overhanging portions the second layer of dielectric material and the substrate.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: October 29, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Gary Hong
  • Patent number: 5569956
    Abstract: An interposer between the leads of a leadframe and the ends of wires connected to an integrated circuit die is described herein. The interposer may consist a polyimide tape or other insulating material with conductive traces formed thereon, each trace electrically connecting an inner bonding pad to an outer bonding pad formed on the tape. The outer bonding pads are generally arranged around the periphery of the interposer and are bonded to respective ends of the leadframe. An integrated circuit die is placed in approximately the center of the interposer surrounded by the inner bonding pads. An automatic bonder then bonds wires to the bonding pads on the die and to the inner bonding pads on the interposer. The die is now electrically connected to the leadframe via the traces on the interposer.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: October 29, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Satya N. Chillara, Jaime A. Bayan
  • Patent number: 5567962
    Abstract: A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate electrode provided on the channel region with a gate insulator therebetween, the gate electrode having at least two opposing portions; and an electrically breakable memory element provided on one of the main electrode regions.
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: October 22, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mamoru Miyawaki, Akira Ishizaki, Genzo Momma, Hiroshi Yuzurihara, Tetsunobu Kohchi
  • Patent number: 5567977
    Abstract: A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: October 22, 1996
    Assignee: SGS- Thomson Microelectronics, S.A.
    Inventor: Jean Jimenez
  • Patent number: 5567958
    Abstract: A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: October 22, 1996
    Assignee: Motorola, Inc.
    Inventors: Marius Orlowski, James D. Hayden, Bich-Yen Nguyen
  • Patent number: 5565691
    Abstract: In a thin film semiconductor device having a substrate (1), an active layer (3, 6, 9), a gate insulation layer (4), and a gate electrode (5), the active layer is produced through the steps of producing an amorphous silicon layer on said substrate through a CVD process by using polysilane Si.sub.n H.sub.2(n+1), n is an integer, with added chlorine gas, and effecting solid phase growth on to said amorphous silicon layer. The addition of chlorine in producing the amorphous silicon layer makes it possible to produce the amorphous silicon layer at a lower temperature and at a rapid growth rate. A thin film semiconductor device thus produced has the advantages of high mobility and low threshold voltage.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: October 15, 1996
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Michio Arai, Isamu Kobori
  • Patent number: 5565698
    Abstract: A protection structure for integrated circuits with an n-channel MOS field-effect transistor has a more stable bipolar state, with the change to the bipolar state occurring fast. Below the drain region and the drain contact region an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide the electrically conductive connection between the drain region and the drain contact region. When a positive voltage pulse is applied to the drain contact region, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage. The conductor paths are typically connected to ground. The n-well forms a series resistor between the drain region and the drain contact region of the respective transistor. It also forms a pn junction between the drain region and the channel, the collector pn junction, which extends deep into the substrate.
    Type: Grant
    Filed: July 6, 1995
    Date of Patent: October 15, 1996
    Assignee: Deutsche Itt Industries GmbH
    Inventor: Cornelius Obermeier
  • Patent number: 5565708
    Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: October 15, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiko Ohsaki, Sumio Yamaguchi, Atsushi Ishii, Kazuyoshi Maekawa, Masahiko Fujisawa
  • Patent number: 5565990
    Abstract: A photographic color temperature meter capable of measuring light including stationary light and flash light. The meter controls timing of light measurements so that light measurement is performed during the time when stationary light and flash light are included and when only stationary light is included. Thereafter, calculation of color temperature only of flash light is performed.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: October 15, 1996
    Assignee: Minolta Camera Kabushiki Kaisha
    Inventors: Norihisa Hosoi, Seiki Yamaguchi, Mikio Uematsu, Yoshihiro Okui
  • Patent number: 5563433
    Abstract: A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell.Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: October 8, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Nagata, Hiroyuki Yoshida, Takayuki Niuya, Yoshihiro Ogata
  • Patent number: 5563427
    Abstract: In the formation of a thin-film transistor (620) capable of improving the OFF current characteristic, first, all ions (arrow Ion-1) generated from a mixed gas (doping gas) containing 5% PH.sub.3 with the remainder being H.sub.2 gas are implanted to a polycrystalline silicon film (604) at an approximately 80 keV energy level to achieve a P.sup.+ ion dose in the range from 3.times.10.sup.13 /cm.sup.2 to 1.times.10.sup.14 /cm.sup.2 in the process forming low concentration source-drain areas (602, 603). Next, all ions generated from a doping gas of pure hydrogen (arrow Ion-2) are implanted to the low concentration area (604a) at an approximately 20 keV energy level to achieve an H.sup.+ ion dose from 1.times.10.sup.14 /cm.sup.2 to 1.times.10.sup.15 /cm.sup.2. Then, the impurity is activated by heat treatment of the low concentration area (604a) implanted with impurity for approximately one hour at approximately 300.degree. C. in a nitrogen atmosphere.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: October 8, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Ichio Yudasaka, Minoru Matsuo, Satoshi Takenaka
  • Patent number: 5561320
    Abstract: A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: October 1, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Robert M. Fritzsche
  • Patent number: 5561315
    Abstract: A programmable semiconductor memory with filament or point diodes in the intersections of a matrix system can be manufactured with minimum dimensions and thus with a very high density owing to the absence of alignment tolerances. A possible problem is then posed by the strong leakage currents which may arise during programming owing to punch-through between adjoining diodes. Decreasing the leakage current through the use of a higher background concentration of the region in which these diodes are formed is not possible because this reduces the breakdown voltage of the pn junctions of the diodes too much. According to the invention, a more strongly doped surface zone is provided in the region between the diodes, which zone is situated at least at a distance from the diode points. In a specific embodiment, the zone extends less deeply into the region than do the diodes.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: October 1, 1996
    Assignee: U.S. Philips Corporation
    Inventor: Maarten J. Van Dort
  • Patent number: 5561308
    Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first insulation film formed on the semiconductor substrate, a gate electrode and a second insulation film formed in sequence on the first insulation film, a trench being formed to extend through the second insulation film, the gate electrode and the first insulation film to an interior of the semiconductor substrate. A cylindrical gate insulation film is formed on a surface of the gate electrode which is exposed in the trench. A capacitor insulation film is formed on a surface of the semiconductor substrate exposed in the trench. A cylindrical conductive film is formed inside these insulation films.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Kamata, Jumpei Kumagai
  • Patent number: 5559602
    Abstract: A rotation measuring apparatus has a grating disposed on a cylindrical surface along the circumferential direction thereof, an illuminating system for applying a light beam to a first location on the grating, light emerging from the first location by the application of the light beam from the illuminating system being incident on a second location on the grating, light beams for detection emerging in a plurality of directions from the second location on which the light is incident, a plurality of light receiving elements for detecting the light beams for detection, respectively, the relative rotation information of the grating and the light receiving elements being measured by the detection by the light receiving elements, and light intercepting means for preventing the light beam for detection which should enter at least one of the light receiving elements from entering a different light receiving element.
    Type: Grant
    Filed: March 11, 1993
    Date of Patent: September 24, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masaru Nyui
  • Patent number: 5559316
    Abstract: A semiconductor device with a semiconductor pellet or pellets mounted on a lead frame and a plastic-molded package, which enables a larger scale integration of circuits than the conventional ones to realize down-sizing. A die pad of the leadframe has a first insulator film formed thereon, a patterned interconnection film formed on the first insulator film, and a second insulator film formed on the first insulator film to cover the interconnection film. Bonding pads of the semiconductor pellet are directly bonded through first windows of the second insulator film to the interconnection film, respectively so that the pellet is electrically connected to the interconnection film. Inner leads of the leadframe are electrically connected through second windows of the second insulator film to the interconnection film, respectively. thus, the bonding pads of the semiconductor pellet are electrically connected through the interconnection film to the inner leads, respectively.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: September 24, 1996
    Assignee: NEC Corporation
    Inventor: Yoshiyuki Tomoda
  • Patent number: 5559372
    Abstract: A semiconductor package directly soldering the chip pad to the inner leads and a method for producing the package are disclosed. The chip pad is placed on the bottom surface of an inner lead extending from opposed sides of the chip pad. A plurality of inner lead holes are formed in the interconnection parts between the inner leads and the auxiliary leads. A solder resist film bonded to the lead frame has a plurality of solder resist holes communicating with the inner lead holes. In order to produce the package, a lead pattern is formed and the lead frame is etched using the lead pattern, so that the inner lead holes and the solder resist holes are formed and the inner leads come into direct contact with the chip pad. Thereafter, the chip pad is soldered to the inner leads.
    Type: Grant
    Filed: January 10, 1995
    Date of Patent: September 24, 1996
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Yong T. Kwon
  • Patent number: RE35356
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: October 22, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill