Patents Examined by Robert P. Limanek
  • Patent number: 5557137
    Abstract: A voltage programmable link structure reduces parasitic capacitance by using ion implantation. The voltage programmable link structure includes a first conductive element placed over a substrate. A transformable insulator is deposited over the first conductive element. The transformable insulator material is deposited with an ion implanted layer. A second conductive element is deposited over the ion implanted layer. An electrical path is formed between the first and second conductive elements by applying a voltage between the elements across at least one region of the insulator, such that the insulating material is transformed and rendered conductive to form an electrical signal path.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: September 17, 1996
    Assignee: Massachusetts Institute of Technology
    Inventor: Simon S. Cohen
  • Patent number: 5557149
    Abstract: A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: September 17, 1996
    Assignee: ChipScale, Inc.
    Inventors: John G. Richards, Wendell B. Sander, Donald P. Richmond, II, Hector Flores
  • Patent number: 5557414
    Abstract: A method and apparatus for classifying articles according to their color, wherein a first pair of wavelengths is selected on a plurality of light reflection curves in terms of a reflected light wavelength spectrum. An article to be inspected is illuminated with light comprising the first pair of wavelengths and light reflected therefrom is measured to detect light reflection values corresponding to this first pair or wavelengths. A primary signal is produced, which represents a resulting difference between the detected light reflection values, this signal being indicative of the color of the inspected article. At least one secondary wavelength is selected on the reflected light wavelength spectrum, and the inspected article is illuminated with light comprising this secondary wavelength and light reflected therefrom is measured to produce a secondary signal which is further indicative of the color of the inspected article.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: September 17, 1996
    Assignee: Centre de Recherche Industrielle du Quebec
    Inventors: Gilles Allaire, Gratien Beauchemin, Roger Garceau, Bruno Leclerc
  • Patent number: 5557138
    Abstract: An LC element with a pn junction layer formed near the surface of a p-Si substrate by forming an n.sup.+ region having a predetermined shape and in a portion thereof additionally forming a p.sup.+ region having the same shape, and with first and second electrodes formed over entire length on the surface of this pn junction layer; wherein the two electrodes respectively function as inductors and by using the pn junction layer with reverse bias, a distributed constant type capacitor is formed between these inductors, thereby providing excellent attenuation characteristics over a wide band, a semiconductor device including the LC element, and a method of manufacturing the LC element.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: September 17, 1996
    Inventors: Takeshi Ikeda, Susumu Okamura
  • Patent number: 5557124
    Abstract: Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: September 17, 1996
    Assignee: Waferscale Integration, Inc.
    Inventors: Anirban Roy, Reza Kazerounian
  • Patent number: 5554869
    Abstract: Flash EEPROM cells having merged select/control gates may be formed, so that the portions of the channel regions that correspond to select transistors are formed after spacers are formed but prior to patterning a merged select/control gate layer. Because the portions of the channel regions that correspond to the select transistors are not determined by the patterning of the merged select/control gate layer, misalignment of the mask used to pattern the merged select/control gate layer does not affect the size of the select transistor portion of the channel region. The spacers may be left on over the substrate in the finished devices thereby saving at least one processing step. The memory structure may also be used in other EPROM-type memory cells, such as individually erasable EEPROMs and EPROMs that are not electrically erasable.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: September 10, 1996
    Assignee: Motorola, Inc.
    Inventor: Kuo-Tung Chang
  • Patent number: 5555519
    Abstract: A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: September 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisaburo Takashima, Shigeyoshi Watanabe
  • Patent number: 5554873
    Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Erdeljac, Louis N. Hutter
  • Patent number: 5552626
    Abstract: A semiconductor device with bipolar transistors formed in respective island regions in which collector regions of the bipolar transistors do not need to be pulled up to the top of the corresponding island regions and do not need to be contacted with a collector electrode on the top of the corresponding island regions. First and second semiconductor island regions are formed to be buried in a second insulator formed on a first insulator. First and second bipolar transistors are provided in the first and second island regions, respectively. An interconnection conductor for electrically interconnecting collector regions of the first and second transistors is formed in the second insulator and in contact with the collector regions of the first and second transistors. A common collector electrode formed on a third insulator covering the first and second island regions is electrically connected with the collector regions of the first and second transistors through the interconnection conductor, respectively.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: September 3, 1996
    Assignee: NEC Corporation
    Inventor: Takenori Morikawa
  • Patent number: 5552638
    Abstract: A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the silane and anneal the metal simultaneously. The excess metal overlying the polyimide between the vias is removed by chemical mechanical polishing using the crosslinked silane as a polish stop.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Loretta J. O'Connor, Rosemary A. Previti-Kelly, Thomas J. Reen
  • Patent number: 5550401
    Abstract: Along the column of bonding pad (1), bonding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to extend in a 3-dimensional crossing configuration with respect to the signal lines, and they are connected to the bonding terminal portion of the bus bars, forming the IC package of the LOC type. Between the various bonding terminal portions and the various bonding pads, there exists no main wiring portion of the bus bar. Consequently, bonding wires (6), (7), (8), (9) do not straddle the bus bar principal wiring portion. As a result, when the bonding wire is not elevated, the bonding wire still does not make contact with the bus bar principal wiring portion to cause short circuit; as a result, the reliability is high and the device becomes thinner.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: August 27, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Takayuki Maeda
  • Patent number: 5548145
    Abstract: A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: August 20, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Hamamoto, Takashi Yamada, Yutaka Ishibashi
  • Patent number: 5548160
    Abstract: A structure for attaching a semiconductor wafer section to a lead frame comprises a carrier having an outside surface and an adhesive coating the carrier. Prior to use, the structure can be placed onto spools for easy shipment and storage.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: August 20, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Tim J. Corbett, Walter L. Moden
  • Patent number: 5545922
    Abstract: A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: August 13, 1996
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima, Keiichi Tsujimoto, Nobuaki Sato
  • Patent number: 5543637
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: August 6, 1996
    Assignee: North Carolina State University
    Inventor: Bantval J. Baliga
  • Patent number: 5543650
    Abstract: An electrostatic discharge protection device for protecting the input of a circuit comprises a p-channel MOSFET (P-FET). The n-well with P+ implants of the P-FET provides a functional lateral PNP bipolar transistor that is coupled between the input of the circuit and a supply node of the circuit. Biasing circuitry controls biasing of the gate and n-well body of the P-FET in accordance with the voltage at the input of the circuit.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: August 6, 1996
    Assignee: International Business Machines Corporation
    Inventors: Wai-Ming W. Au, Minh H. Tong
  • Patent number: 5544095
    Abstract: Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: August 6, 1996
    Assignee: Harris Corporation
    Inventors: Charles W. T. Longway, William R. Young
  • Patent number: 5543656
    Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: August 6, 1996
    Assignee: Actel Corporation
    Inventors: Yeouchung Yen, Shih-Oh Chen
  • Patent number: 5543644
    Abstract: An electrical ceramic oxide capacitor utilizable in an integrated circuit memory device, and a method for making same is presented. A transistor is fabricated on a semiconductor substrate according to conventional techniques. A diffusion barrier is deposited over the transistor to protect it from subsequent process steps. Metal contacts are formed to contact the active transistor regions in the substrate, and additional barriers are formed to insulate the metal contacts. In a vertical embodiment, the barriers above the metal contacts can serve as bottom electrodes for the capacitor. In a lateral embodiment, the barriers on the side of the metal contacts serve as electrodes for the capacitor. Electrical ceramic oxide material is deposited between the electrode plates.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: August 6, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Norman E. Abt, Reza Moazzami, Yoav Nissan-Cohen
  • Patent number: 5543663
    Abstract: A first thermal conductive member and a plurality of second thermal conductive members are formed on one major surface of an insulating board. A TCP is mounted on the first thermal conductive member. A heat sink is mounted on the plurality of second thermal conductive members. A third thermal conductive member is formed on the other major surface of the insulating board. A plurality of through holes are formed in the insulating board between the first and third thermal conductive members and between the second and third thermal conductive members. Fourth thermal conductive members are formed in the plurality of through holes. Heat generated by the semiconductor chip of the TCP is conducted to the heat sink through the first to fourth thermal conductive members. Therefore, a semiconductor device with excellent heat dissipation without damaging a semiconductor element can be provided.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: August 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chiaki Takubo