Patents Examined by Roberts Culbert
  • Patent number: 9850403
    Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) abrasive particles, (b) a cobalt accelerator selected from a compound having the formula: NR1R2R3 wherein R1, R2, and R3 are independently selected from hydrogen, carboxyalkyl, substituted carboxyalkyl, hydroxyalkyl, substituted hydroxyalkyl and aminocarbonylalkyl, wherein none or one of R1, R2, and R3 are hydrogen; dicarboxyheterocycles; heterocyclylalkyl-?-amino acids; N-(amidoalkyl)amino acids; unsubstituted heterocycles; alkyl-substituted heterocycles; substituted-alkyl-substituted heterocycles; N-aminoalkyl-?-amino acids; and combinations thereof, (c) a cobalt corrosion inhibitor, (d) an oxidizing agent that oxidizes a metal, and (e) water, wherein the polishing composition has a pH of about 3 to about 8.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains cobalt.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 26, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Steven Kraft, Andrew Wolff, Phillip W. Carter, Kristin Hayes, Benjamin Petro
  • Patent number: 9847211
    Abstract: A method for making a conductive film includes the steps of: depositing a conductive metal film on a substrate to form a metal-coated substrate; depositing a fiber pattern on the conductive metal film of the metal-coated substrate to form a masked substrate, the fiber pattern defining protected metal and exposed metal of the conductive metal film; removing the exposed metal from the conductive metal film of the masked substrate to form a protected conductive film; and removing the fiber pattern from the protected conductive film to expose the protected metal and provide a metal pattern on the substrate. An annealing step con be employed after depositing the fiber pattern to increase the surface area of contact between the fiber pattern and the conductive metal film.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: December 19, 2017
    Assignee: The University of Akron
    Inventors: Yu Zhu, Tianda He
  • Patent number: 9844888
    Abstract: A method for forming a cutting tool includes masking a metal base with one or more masks, the one or more masks including at least one variable permeability mask, and chemically etching the masked metal base to form a blade of the cutting tool.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 19, 2017
    Assignee: Hutchinson Technology Incorporated
    Inventors: Paul V. Pesavento, Peter F. Ladwig, Michael W. Davis, John A. Theget, Kurt C. Swanson, Joel B. Michaletz, Philip W. Anderson, Timothy A. McDaniel
  • Patent number: 9845538
    Abstract: The object of the present invention is to provide: an etching agent for a titanium-based metal on a semiconductor substrate, which suppresses decomposition of hydrogen peroxide, has a long liquid service life, and has less need for controlling the concentration of hydrogen peroxide in the etching agent, even in the cases where the etching agent is used for a semiconductor substrate having the titanium-based metal and a metallic copper or a metal alloy; an etching method; and an etching agent preparation liquid for use by mixing with hydrogen peroxide.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: December 19, 2017
    Assignee: WAKO PURE CHEMICAL INDUSTRIES, LTD.
    Inventors: Takahiro Yokomizo, Hiroyuki Tsurumoto, Masahiko Kakizawa
  • Patent number: 9837279
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes bringing a first catalyst into contact with a workpiece to form an oxide film on a surface of the workpiece, and bringing a second catalyst different from the first catalyst and the oxide film into contact with each other or moving the second catalyst and the oxide film closer to each other to elute the oxide film into a treatment liquid.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 5, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Akifumi Gawase, Yukiteru Matsui, Takahiko Kawasaki
  • Patent number: 9834705
    Abstract: Provided are a slurry for polishing tungsten and a method of polishing a substrate. The slurry according to an exemplary embodiment includes an abrasive configured to perform polishing and include particles having a positive zeta potential, a dispersant configure to disperse the abrasive, an oxidizer configured to oxidize a surface of the tungsten, a catalyst configured to promote oxidation of the tungsten, and a selectivity control agent configured to control a polishing selectivity and include an organic acid containing a carboxyl group. According to the slurry of the exemplary embodiment, a polishing selectivity between the tungsten and the insulation layer may be improved by suppressing a polishing rate of the insulation layer.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 5, 2017
    Assignee: UBMATERIALS INC.
    Inventor: Jin Hyung Park
  • Patent number: 9831068
    Abstract: A method activates the inner surface of a substrate tube via plasma etching with a fluorine-containing etching gas. An exemplary method includes the steps of (i) supplying a supply flow of gas to the interior of a substrate tube, wherein the supply flow includes a main gas flow and a fluorine-containing etching gas flow, (ii) inducing a plasma via electromagnetic radiation to create a plasma zone within the substrate tube's interior, and (iii) longitudinally reciprocating the plasma zone over the length of the substrate tube between a reversal point near the supply side and a reversal point near the discharge side of the substrate tube. The flow of the fluorine-containing etching gas is typically provided when the plasma zone is near the supply side reversal point.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 28, 2017
    Assignee: Draka Comteq, B.V.
    Inventors: Igor Milicevic, Gertjan Krabshuis, Mattheus Jacobus Nicolaas Van Stralen, Peter Gerharts, Johannes Antoon Hartsuiker
  • Patent number: 9828527
    Abstract: Described is a chemical-mechanical polishing (CMP) composition comprising the following components: (A) surface modified silica particles having a negative zeta potential of ?15 mV or below at a pH in the range of from 2 to 6 (B) N,N,N?,N?-tetrakis-(2-hydroxypropyl)-ethylenediamine or methanesulfonic acid (C) water (D) optionally one or more further constituents, wherein the pH of the composition is in the range of from 2 to 6.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 28, 2017
    Assignee: BASF SE
    Inventors: Yongqing Lan, Peter Przybylski, Zhenyu Bao, Julian Proelss
  • Patent number: 9831095
    Abstract: A method for performing selective etching of a semiconductor material in solution having the following successive steps: a) providing a substrate having a layer of amorphous semiconductor material to be etched and a layer of crystalline semiconductor material; b) oxidizing the surfaces of the layers of amorphous semiconductor material and of crystalline semiconductor material so as to form a first protective layer at the surface of the amorphous semiconductor material and a second protective layer at the surface of the crystalline semiconductor material; c) etching the first protective layer and the layer of amorphous semiconductor material with an alkaline etching solution, the etch rate v1 of the first protective layer being higher than the etch rate v2 of the second protective layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: November 28, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Virginie Loup, Pascal Besson
  • Patent number: 9818610
    Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 14, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
  • Patent number: 9818584
    Abstract: An inductively coupled plasma source for a focused charged particle beam system includes a conductive shield within the plasma chamber in order to reduce capacitative coupling to the plasma. The internal conductive shield is maintained at substantially the same potential as the plasma source by a biasing electrode or by the plasma. The internal shield allows for a wider variety of cooling methods on the exterior of the plasma chamber.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: November 14, 2017
    Assignee: FEI Company
    Inventors: Thomas G. Miller, Shouyin Zhang
  • Patent number: 9805940
    Abstract: A plasma processing method includes forming plasma in a processing chamber; and performing etching to a film to be processed of a film structure that has previously been disposed on an upper surface of a wafer that includes a plurality of film layers. The film structure includes: a lower film including at least one film layer and a groove structure; and an upper film including at least one film layer that covers an inside and an upper end of the groove structure. The plasma processing method includes: removing the upper film by etching until an upper end of the groove structure of the lower film is exposed; performing etching to a film layer of the upper film inside the groove structure; and determining an end point by using a value of thickness of the film layer inside the groove structure of the lower film upon completion of the removing.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 31, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kousuke Fukuchi, Shigeru Nakamoto, Tatehito Usui, Satomi Inoue
  • Patent number: 9802221
    Abstract: A method including: a first step of forming a mask member having a structure in which a magnetic metal member provided with through-holes is in tight contact with one surface of a film; a second step of forming a plurality of preliminary opening patterns by subjecting the film to penetration processing by irradiating laser beams at predetermined regular positions in the plurality of through-holes; and a third step of performing laser processing so as to form each opening pattern over the corresponding preliminary opening pattern, is provided.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 31, 2017
    Assignee: V Technology Co., Ltd.
    Inventor: Michinobu Mizumura
  • Patent number: 9796882
    Abstract: Described are compositions useful in methods for chemical-mechanical processing a surface of a substrate, especially a substrate that contains dielectric material, wherein the composition contains cyclodextrin and an alkylamine.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 24, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Tina Li
  • Patent number: 9786526
    Abstract: A method and an apparatus for etching microstructures and the like that provides improved selectivity to surrounding materials when etching silicon using xenon difluoride (XeF2). Etch selectivity is greatly enhanced with the addition of hydrogen to the process chamber.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: October 10, 2017
    Assignee: MEMSSTAR, LIMITED
    Inventor: Anthony O'Hara
  • Patent number: 9779956
    Abstract: A method for selectively etching SiO and SiN with respect to SiGe or Si of a structure is provided. A plurality of cycles of atomic layer etching is provided, where each cycle comprises a fluorinated polymer deposition phase and an activation phase. The fluorinated polymer deposition phase comprises flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas, forming the fluorinated polymer deposition gas into a plasma, which deposits a fluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas. The activation phase comprises flowing an activation gas comprising an inert bombardment gas and H2, forming the activation gas into a plasma, wherein the inert bombardment gas activates fluorine in the fluorinated polymer which with the plasma components from H2 cause SiO and SiN to be selectively etched with respect to SiGe and Si, and stopping the flow of the activation gas.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 3, 2017
    Assignee: Lam Research Corporation
    Inventors: Xin Zhang, Alan Jensen, Gerardo Delgadino, Daniel Le
  • Patent number: 9780000
    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, including at least one step of forming a protective layer covering the gate; depositing a layer comprising carbon, said layer being disposed distant from said transistor; modifying the protective layer to form a modified protective layer; forming a protective film on the layer comprising carbon; removing the protective film on surfaces of the protective film that are perpendicular to a main implantation direction; selectively removing the layer comprising carbon; and at least one step of selectively removing the modified protective layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Maxime Garcia-Barros
  • Patent number: 9771266
    Abstract: A method for processing carbon nanotubes includes positioning in a treatment chamber of a carbon nanotube processing apparatus a substrate having multiple carbon nanotubes bundled together and oriented substantially perpendicular to a surface of the substrate, and introducing a microwave into the treatment chamber from a planar antenna having multiple microwave radiation holes such that plasma of an etching gas is generated and that the plasma etches the carbon nanotubes starting from one end of the carbon nanotubes bundled together.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: September 26, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Matsumoto, Osayuki Akiyama
  • Patent number: 9768025
    Abstract: A method of fabricating a semiconductor device includes forming a target layer on a substrate, forming a plurality of reference patterns at uniform intervals on the target layer, forming a plurality of spacers on the side surfaces of the reference patterns, forming a plurality of filling patterns in spaces left between the spacers, forming a surface-modified filling pattern by performing a first surface treatment on a portion of the plurality of filling patterns, forming a surface-modified reference pattern by performing a second surface treatment on a portion of the plurality of reference patterns, and removing the plurality of filling patterns and the plurality of reference patterns and leaving the surface-modified filling pattern and the surface-modified reference pattern on the target layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongkong Siew, Sung-Yup Jung
  • Patent number: 9768024
    Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen, Tien-I Bao