Abstract: A field effect transistor with improved operation speed and reduced noise includes a drain electrode disposed on a channel layer with a contact layer interposed therebetween, a source electrode, and a gate electrode disposed between the drain and source electrodes. A resonant tunneling diode is disposed between the source electrode and the channel region for supplying hot electrons to the channel layer beneath the gate electrode.

Abstract: A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.

Abstract: In a thin film transistor formed by a gate electrode formed on a transparent insulating substrate, a semiconductor active layer opposing the gate electrode, a drain electrode, and a source electrode connected to a transparent pixel electrode, an optical shield layer is located so as to approximately surround the semiconductor active layer.

Abstract: A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N.sup.+ silicon, an N.sup.- silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N.sup.- silicon layer. The THBT base is layer of P.sup.+ SiGe grown on the superlattice. The THBT Emitter is a second Si/SiGe Superlattice grown on the base layer. An N.sup.- silicon layer is grown on the emitter superlattice. A layer of N.sup.+ GaP grown on that N.sup.- Si layer. The base is formed, first, by etching a rectangular groove through the emitter, ion implanting dopant into the base layer to form an extrinsic base, etching a V shaped groove into the extrinsic base and, then, filling the grooved base with doped polysilicon.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: The present invention is directed to an improved system for inspection of microelectronic assemblies, including chips and interconnection elements such as wires, ball bonds, and wedge bonds contained therein. This system includes a high speed illumination subsystem, a dual magneification video camera sensor subsystem, a commercial machine vision system supported by a video display and printer, a three dimensional transport stage for moving the microcircuit under inspection, and a computer controller for operational control under unique software of all of the above system elements. The illumination subsystem includes formation of multiple light rings starting with light generated by a tungsten lamp, collimation by a condenser lens, then passage through a liquid crystal light valve having a plurality of circular active transmission areas.

Abstract: A semiconductor bond pad prevents cratering by including an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

Abstract: An electro-mechanical assembly includes a high power IC package and a low power IC package which are mounted with a space between them on a single substrate. Both of these IC packages have flat top surfaces which dissipate heat; and due to various manufacturing tolerances, those surfaces are non-coplanar with respect to each other. To cool these two IC packages, a single heat sink is provided which has a thin flat core that overlies both of the IC packages as well as the space between them, and cooling fins extend from the top of the core.

Abstract: A semiconductor device (10) includes a lead frame (12) having tie bars (16). In one form of the invention, the tie bars are used to support a semiconductor die (20) to alleviate package cracking problems caused by stress and to provide a universal lead frame which is suitable for use with many different die sizes. In another embodiment, a semiconductor device (45) includes a lead frame (40) having a mini-flag (42) to accomplish these same objectives.

Abstract: A method and apparatus is provided for ensuring that an image projected upon a visual display device is properly aligned with the viewing surface of the display device. Important to achieving the proper alignment is the use of a fluorescent ink which is visible only when illuminated under ultraviolet light. Use of the fluorescent ink allows a pattern of reference points, constituting an alignment pattern, to be permanently marked directly on the viewing surface of the visual display device, for example. Since the alignment pattern is permanently marked and is visible only when illuminated with ultraviolet light, alignment between the image and the display device can be immediately determined without the aid of additional equipment such as is employed by previously known image alignment systems.

Abstract: A description is given of an apparatus for the contact-free, spatial measurement of a poorly accessible, three-dimensional object (9) optically by taking surface photographs, having an optic ray source, a recording unit (10, 11) for recording optic rays (15, 18, 19, 25), and an evaluation unit for the evaluation of the data transmitted by the optic rays.

Abstract: A semiconductor module having good heat dissipation and large current density includes an insulating substrate having a first group of wiring layers, a plurality of electronic components such as IC chips mounted on the insulating substrate and having bonding pads, an insulating sheet provided above the insulating substrate to cover the electronic components and having a second group of wiring layers, and a plurality of apertures formed in the insulating sheet and electrically connecting the first and second groups of wiring layers and the bonding pads to one another. The first group of wiring layers has a larger current capacity than the second group of wiring layers.

Abstract: A thin MCM packaging structure and technique is provided in which a thin film decal interconnect circuit is fabricated on a thin aluminum wafer. The thin-film decal interconnect employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die. A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities to hold one or more die to be mounted on the MCM structure. The die are oriented with their pads in contact with contact pads on the thin-film decal interconnect to which they are bonded and the cavities are filled with a liquid encapsulant and cured.

Abstract: A sample liquid flow containing particle components such as blood and urine is illuminated with light, and signals from particles are detected, and the particles are thereby analyzed. In this apparatus, using a prism or a diffraction grating, spectra of light signals are obtained, and more specific information regarding the particles is obtained. The fluorescence from the particles is separated by a prism or diffraction grating and classified into wavelength, the intensity of the obtained fluorescence spectra is amplified by an image intensifier, and the intensity is measured for each wavelength by an image sensor.

Abstract: A screening device can be used to test ring laser gyro performance at numerous points during the gyro assembly. This performance testing can be done without physically attaching electrical connections thereto and at a point prior to the attachment of readout sensors and/or dither motors. This screening device provides a valuable tool in identification of problems related to gyro performance which may be incurred during the assembly of the gyroscope.

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: A high performance ball grid array is disclosed in which a ball grid array is modified to include a body having a recessed central cavity. The inclusion of a central cavity allows the die to be mounted on the same side of the package in which the solder balls are located. Since the die is mounted on the same side as that of the solder balls, only one set of leads is needed to electrically connect the die to the solder balls, thus requiring only one layer of electrically conductive material within the package, as opposed to conventional ball grid array packages which required two metal layers. In addition, since only one metal layer is needed, the present invention is able to operate without the use of electrically conductive vias. The die is connected via wire bonds to bonding areas located on the package. Each of the of bonding areas is substantially co-planar, and each bonding area is located at a different distance from one edge of the central cavity, thereby forming a staggered arrangement.

Abstract: An integrated circuit device having an array of flexible leads attached to the bottom of an integrated circuit package. There is provided a sheet of electrically conductive material. A plurality of slots are punched into the sheet, such that there is formed a plurality of beams. The beams are then bent into a spring shape. The sheet is placed over an integrated circuit package which has an array of contact pads extending across a bottom surface of the package. The beams are aligned and attached to the contact pads. The beams are then cut and separated from the remainder of the sheet. The sheet is removed, wherein there is constructed an integrated circuit package that has a two dimensional array of flexible leads.

Abstract: When a ZnSe, ZnTe or ZnSSe or Zn.sub.1-a Mg.sub.a S.sub.b Se.sub.1-b (0<a<1, 0<b<1) layer provided on a Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y (0<x<1, 0<y<1, a<x) layer is selectively etched by a dry etching method such as an RIE method, the Zn.sub.1-x Mg.sub.x S.sub.y Se.sub.1-y layer is used as an etching stopping layer. Thus, selective etching of the ZnSe, ZnTe, ZnSSe or Zn.sub.1-a Mg.sub.a S.sub.b Se.sub.1-b layer can be conducted with excellent controllability and reproducibility.