Patents Examined by Rolf Hille
  • Patent number: 5508534
    Abstract: A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X .ltoreq.5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X.ltoreq.5 permits a first main electrode to be formed non-defectively without being affected by the ground pattern including the insulating layers.
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: April 16, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominga, Katsuomi Shiozawa
  • Patent number: 5508564
    Abstract: A semiconductor device is fabricated having contact holes formed in an interlayer insulator and on impurity diffusion regions positioned on either side of an isolator, The contact holes are arranged so as not to be disposed along a shortest line path across the isolator. This arrangement isolating interval and provides a structure which can realize higher packing density and improved reliability.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: April 16, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-pil Lee, Yong-jik Park
  • Patent number: 5508553
    Abstract: A transversal bipolar transistor is structured to have a single crystal semiconductor film provided on a single crystal semiconductor region which is provided on a semiconductor substrate. The semiconductor substrate is of a first conductivity type, and the single crystal semiconductor region is of a second conductivity type which is opposite to the first conductivity type. The single crystal semiconductor film is divided in the transversal direction into a central portion of the second conductivity type for a base region and left and right portions of the first conductivity type for emitter and collector regions. The transversal bipolar transistor may be integrated with a vertical bipolar transistor commonly on the semiconductor substrate.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: April 16, 1996
    Assignee: NEC Corporation
    Inventors: Satoshi Nakamura, Tsutomu Tashiro
  • Patent number: 5508559
    Abstract: A method for forming a power circuit package (45) having a porous base structure (20) electrically isolated from a first porous die mount (21) and a second porous die mount (22) by a dielectric material (29). The porous base structure (20) is bonded to a second surface of the the dielectric material (29) whereas the first porous die mount (21), and the second porous die mount (22) are bonded to a first surface of the dielectric material (29). Simultaneous with the bonding step, the porous base structure (20), the first porous die mount (21), and the second porous die mount (22) are impregnated with a conductive material. Semiconductor die (32, 33, 34, and 35) are bonded to the impregnated die mounts. The semiconductor die (32, 33, 34, and 35) are then encapsulated by a molding compound.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: April 16, 1996
    Assignee: Motorola, Inc.
    Inventors: Samuel J. Anderson, Guillermo L. Romero
  • Patent number: 5506451
    Abstract: An N-InP buffer layer is deposited on an N.sup.+ -InP substrate, an InGaAs light-absorbing layer is deposited on the buffer layer, an N.sup.- -InP cap layer is deposited on the light-absorbing layer, and a P-type impurity region is formed in the light-absorbing layer and the cap layer. Next, a masking film is formed on the cap layer, and with this masking film serving as a mask, the cap layer, the light-absorbing layer, the buffer layer are etched, thus forming a P-type electrode forming region and an N-type electrode forming region. Next, an insulating film is provided for the periphery portion of the P-type impurity region of the cap layer. Electrode pads having a laminated structure is formed respectively on the P-type and N-type electrode forming regions, and a non-metal member is formed on the insulating film and on the surface, the periphery and the side surface of the electrode pad of the P-type electrode.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Hyugaji
  • Patent number: 5506420
    Abstract: Improved bio-electronic devices in which a layer of a polyhydroxy oligomer is provided between the surface of a semiconductor material and an electronically active biochemical molecule which is designed to be bound to the semiconductor surface to provide an electronic device. The layer of polyhydroxy oligomer functions as a biochemical stabilization layer to prevent denaturization of the electronically active biochemical molecule.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: April 9, 1996
    Assignee: The Regents of the University of California
    Inventors: Nir Kossovsky, Andrew Gelman, H. James Hnatyszyn, Samir Rajguru
  • Patent number: 5504368
    Abstract: A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an injector of an IIL are integrated on a P-type silicon substrate. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. Since both the superhigh speed vertical NPN transistor having a reverse direction structure and the superhigh speed vertical NPN transistor are self-aligned, the superhigh speed vertical NPN transistor and the IIL device may be integrated on the same chip. In addition, the intrinsic base layer of the vertical NPN transistor having a reverse direction structure is deeper in junction than the base layer of the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: April 2, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shigeki Sawada
  • Patent number: 5504376
    Abstract: In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: April 2, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Natsuo Ajika, Toshiaki Ogawa, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 5504371
    Abstract: A ceramic element is formed by a rare earth and transition element oxide such as LaCoO.sub.3. The ceramic element is substantially isolated from the atmosphere by a case base, a case, etc.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: April 2, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hideaki Niimi, Kenjiro Mihara, Yuichi Takaoka
  • Patent number: 5502334
    Abstract: A metal wiring is composed of an electroconductive adhesive layer formed on the inner wall of a contact hole provided in a dielectric film and on the surface of the above mentioned dielectric film, a first metal wiring arranged on the adhesive layer and filling the contact hole, and a second metal wiring which is made of a metal which is different from that of the first metal wiring and is formed on the above mentioned first metal wiring. The first metallic film formed on the above mentioned first metal wiring is formed by, for example, the blanket tungsten-CVD method.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: March 26, 1996
    Assignee: Sony Corporation
    Inventor: Keiji Shinohara
  • Patent number: 5500560
    Abstract: In a semiconductor device having a first conductor layer (25) formed on a first insulator layer (23) and a second insulator layer (29) formed on the first conductor layer, a second conductor layer (31) has a primary conductor film (35) formed on the second insulator layer, a secondary conductor film (37) formed on the primary conductor film, and a ternary conductor film (63) formed on the secondary conductor film. The second insulator layer has a recessed surface (29b) which defines a contact perforation exposing a predetermined area of an upper surface (25a) of the first conductor layer. The secondary conductor film is further formed on the recessed surface and the predetermined area. The primary conductor film has a primary resistance value. The secondary conductor film has a secondary resistance value which is lower than the primary resistance value.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: March 19, 1996
    Assignee: NEC Corporation
    Inventor: Isao Kano
  • Patent number: 5500554
    Abstract: A bipolar transistor with a structure such that it is possible to reduce the parasitic capacity without sacrificing improvements in cut-off frequency f.sub.T, in which a P.sup.+ -type polycrystalline silicon film 122A is provided on the side wall of an opening 143A which is provided in a silicon nitride film 152A serving as the middle layer of a laminated insulation film 107A, and, a P-type single crystal silicon layer 121A constituting the intrinsic base region is connected to a P.sup.+ -type polycrystalline silicon film 111 which is a base drawing electrode via a thin P.sup.+ -type polycrystalline silicon film 123A.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: March 19, 1996
    Assignee: NEC Corporation
    Inventor: Fumihiko Sato
  • Patent number: 5500555
    Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: March 19, 1996
    Assignee: LSI Logic Corporation
    Inventor: Tom Ley
  • Patent number: 5500541
    Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: March 19, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohide Terashima, Masanori Fukunaga
  • Patent number: 5498898
    Abstract: A semiconductor device comprises a semiconductor substrate a field-shield electrode made of a thin film of at least one of polysilicon and amorphous silicon and formed on a surface of an element-isolation region of the substrate with an insulating film interposed therebetween for defining an active region in the substrate and a transistor having a gate electrode formed on a surface of the active region of the substrate with a gate insulating film interposed between the substrate and the gate electrode wherein the field-shield electrode is connected to a predetermined potential and the insulating film has a thickness of 5 nm-10 nm which is less than a thickness of the gate insulating film of the transistor.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: March 12, 1996
    Assignee: Nippon Steel Corporation
    Inventor: Koichiro Kawamura
  • Patent number: 5498903
    Abstract: An integrated circuit package of the surface-mountable type within which a battery is mounted is disclosed. Battery leads extend from the side of the package body opposite that which is adjacent the circuit board when mounted, and between which a conventional battery may be placed. Standoffs are located on the package body for supporting the battery above the package body, so that a gap is present therebetween. A housing is attached to the package over the battery, and has standoffs attached to its inner surface so that a gap is also present between the housing and the battery. The gaps may be air gaps or filled with a low thermal conductivity material. The gaps thermally insulate the battery from the package body and housing, so that the circuit may be subjected to solder reflow mounting to a circuit board, while insulating the high temperatures from the battery.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: March 12, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: D. Craig Dixon, Michael J. Hundt
  • Patent number: 5498893
    Abstract: A semiconductor device includes a semiconductor layer which has a first surface, and a second surface which is comparatively lower than the first surface. The semiconductor device also has a first material layer formed over the second surface, which includes a first inorganic material which has a hardness exceeding that of the semiconductor layer. The semiconductor device also includes a second material layer which has a hardness less than that of the first material layer, and which is formed in a gap between a sidewall of the first material layer and a sidewall between the first and second surfaces. The first surface of the semiconductor layer is formed by lapping until the first surface of the semiconductor layer is impeded by the first material layer so that the first surface of the semiconductor layer is substantially flush with a top surface of the first material layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 12, 1996
    Assignee: Fujitsu Limited
    Inventors: Shouji Usui, Taketoshi Inagaki, Kiyomasa Kamei, Takeshi Matsutani, Kazunori Imaoka
  • Patent number: 5498908
    Abstract: A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: March 12, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nakabayashi, Takashi Uehara, Akihira Shinohara
  • Patent number: 5497028
    Abstract: An LC element and an semiconductor device comprising a second electrode having a predetermined shape formed in direct contact with the surface of a semiconductor substrate, and a first electrode having a predetermined shape formed interspaced by an insulation layer on the semiconductor substrate surface; and a method of manufacturing the LC element. A channel formed along the first electrode on application of a predetermined gate voltage to a control electrode connected to the first electrode and the second electrode respectively function as inductors, while a distributed constant type capacitor is also formed between these; and by using the channel as a signal transmission line, the LC element and a semiconductor device give excellent attenuation characteristics. The LC element and semiconductor device are easily manufactured, while parts assembly work in subsequent processing can be abbreviated, formation as a portion of an IC or LSI device is possible, and characteristics can also be controlled.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: March 5, 1996
    Inventors: Takeshi Ikeda, Susumu Okamura
  • Patent number: 5497030
    Abstract: A lead frame includes a chip mount board, on which a semiconductor chip is to be mounted, and a lead frame body. The chip mount board is made of an electrically insulated substrate and conductive patterns are formed on said insulated substrate. The lead frame body includes a plurality of leads arranged side by side to constitute a co-planar structure and used as signal leads and as ground or power supply leads arranged at the sides of said signal lead. The signal lead has a predetermined width and predetermined distances to the adjacent ground or power supply leads, and the width and distances are determined in such a manner that the signal lead has a desired characteristic impedance. A semiconductor chip is mounted on said chip mount board, electrically connected the conductive patterns on the chip mount board and, hermetically sealed with resin.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: March 5, 1996
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yukiharu Takeuchi