Patents Examined by Ron Pompey
  • Patent number: 8980653
    Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Venkat Ananthan
  • Patent number: 8975635
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8975137
    Abstract: A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 10, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8962421
    Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Gopal Srinivasan, Andy Wei, Dinesh Somasekhar, Ali Keshavarzi, Subi Kengeri
  • Patent number: 8962400
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8956929
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 8957509
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: February 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8951819
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, Aparna Iyer
  • Patent number: 8951903
    Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
  • Patent number: 8932904
    Abstract: A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Shintaro Sato
  • Patent number: 8916433
    Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Baars, Sven Beyer
  • Patent number: 8912071
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8912529
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8912042
    Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: December 16, 2014
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima, Ryuji Fujii
  • Patent number: 8912054
    Abstract: A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 16, 2014
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroshi Hayashi, Takahiro Kawashima, Genshiro Kawashi
  • Patent number: 8906809
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The structure includes a lid encapsulating at least one chip mounted on a chip carrier; at least one seal shim fixed between the lid and the chip carrier, the at least one seal shim forming a gap between pistons of the lid and respective ones of the chips; and thermal interface material within the gap and contacting the pistons of the lid and respective ones of the chips.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Beaumier, Steven P. Ostrander, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 8900927
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The method includes contacting pistons of a lid with respective ones of chips on a chip carrier. The method further includes separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier. The at least one seal shim has a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier. The method further includes dispensing thermal interface material within the gap and in contact with the chips. The method further includes sealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Beaumier, Steven P. Ostrander, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 8866202
    Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Lam Research Corporation
    Inventors: S. M. Reza Sadjadi, Zhi-Song Huang
  • Patent number: 8853005
    Abstract: When forming a conductive film by a method comprising sputtering after grinding the back surface of a semiconductor substrate, in order to avoid discharge from a part of an adhesive flown out at the outer periphery of the substrate, wherein the adhesive is used to fix the substrate to a support during grinding, at least the substrate end or the adhesive is removed after grinding the semiconductor substrate and before forming the conductive film, so that a gap between the substrate end and the adhesive may have a predetermined size.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: October 7, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Seiya Fujii
  • Patent number: RE45286
    Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Olivier Le Neel, Peyman Sana, Loi Nguyen, Venkatesh Mohanakrishnaswamy