Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Abstract: An aviation weather information dissemination system and method involves regional weather-information accumulating and interpreting stations (12A-O) located throughout a geographic area (10). Each regional weather-information and interpreting station communicates with sources (16, 20 and 24) of current weather information peculiar to widely scattered geographic locations, within the geographic area (10). The system also includes a plurality of terminals which communicate with the regional weather-information accumulating and interpreting stations (12) via telephone lines, with each regional station serving particular terminals (14). The regional stations (12), in response to receiving origin and destination points of flights from said terminals (14), compute tentative flight paths between said origin and destination points and provide weather information to the terminals (14) in particular sequences relative to the origins and destinations.

Abstract: A memory management system is structured for use with a self-contained microprocessor to form a multi-user computer. The system operates to establish user and kernel modes each having different operating permissions. When the system is operating in the user mode, certain of the fixed functions of the microprocessor, such as interrupt-off and halt, are blocked from enablement by any user. The system is designed having multiple memory maps, some accessible when in the user mode and all accessible from the kernel mode.

Abstract: A digital computer system in which data operands are represented by names. Each procedure includes a name table, and means are provided to employ the name table to resolve the names into storage addresses at run time. The system also has the ability to run any of a plurality of S-Languages (an S-Language being conceptually similar to a machine language but of higher order); each S-Language can be optimally tailored to a high-order user language. Each procedure includes a dialect code which indicates the dialect of S-Language to which the instructions in the current procedure belong, and the system has provision to execute each procedure accordingly.

Abstract: An optical passive bus control system includes an access coordinator and control unit which is connected to the passive network in the same manner as other connected devices of the network. The access coordinator control means is located spatially close to the optical mixer, over connecting light wave guides which are as short as possible. The access coordinator and control unit contains a collision recognition device for recognizing an access collision, and includes means for implementing an asynchronous access operating mode in response to a collision recognition. A switch means is provided for emitting a signal to the bus, signifying a change to a synchronous operating mode in which no access collisions can occur.

Abstract: An integrated structure including a program counter, a memory management structure and an incrementer interconnected by an internal bus such that the logic value of the program counter may be read into the memory management register and the program counter can be incremented depending upon the value of the pre-incremented program counter logic level and an increment signal from the previous stage. External access to the program counter and the memory management register are provided by external buses. A sense amplifier is also provided so as to maintain the value of the pre-incremented program counter on the internal rail allowing the memory management register to be disconnected therefrom during the increment cycle.

Abstract: A device for digital acquisition, storage and processing of time-dependent data signals, especially for the accumulation of interferograms delivered by spin resonance and infrared spectrometers, comprises an A/D converter; a main memory having random access; a disk storage; a data channel connecting the A/D converter with the main memory which data channel contains a pointer register and a word counter and carries out the direct transfer of words delivered by the A/D converter to that area of the main memory indicated by the contents of the pointer register, the number of words being defined by the contents of the word counter; and a central unit which loads the pointer register and the word counter at the beginning of each measurement period and activates the transfer of word blocks from the main memory to the disk storage and vice versa.

Abstract: Text editing and subsequent reformatting of a document is performed in two separate stages run as two parallel processes with different priorities. The editing of text is performed as a high priority process directly on a selected portion of the document previously copied under control of edit/format control logic 7 from a document store 5 into a refresh buffer 3. The editing process takes each keystroke as it is received by control logic 7 from keyboard 8 and enters it into buffer 3. The contents of the buffer 3 are directly mapped onto a display screen 2 so that the updated portion of the document is immediately seen by the operator. Should insufficient space be available in buffer 3 to accommodate an edited line of text, space is made available by controlled wordspill of text from the line into auxiliary storage prior to execution of the editing operation.

Abstract: There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.

Abstract: Arrangement for reading out defined data from a digital switching device with asynchronous control signals for sequential switching of the device and transferring of the data from another switching device. The arrangement includes circuits for applying a signal to the other switching device for sequentially switching the other device and a buffer memory for temporarily storing state variables of the first switching device and circuits for applying a read pulse to the second-mentioned switching device together with circuits for transferring the state variables stored in the buffer memory to the first-mentioned switching device.

Abstract: A present position display device suitable for use on automobiles or the like vehicles, having a head member provided with a light-emitting element and a light-receiving element; a driving mechanism for driving the head member in the directions of an X and Y-axes; a mechanism for rotationally driving the driving mechanism; a sheet pack detachably mounted in the vicinity of and in parallel with the plane of movement of the head member; and a map transferrably disposed in the sheet pack; whereby the present position of the vehicle is indicated by the light coming from the light-emitting element on the map. Means are provided to read codes of specific positions marked on the map and to make an indication of the specific position as desired.

Abstract: A mode setting control system comprising a one-chip microprocessor and a mode setting circuit provided outside the microprocessor. The mode setting circuit comprises mode designating switches, diodes and a flip-flop. Data representing the mode designated by the switches is written into the one-chip microprocessor through I/O pins. After the one-chip microprocessor has been brought out of the reset state, an ADR signal is supplied from the one-chip microprocessor through an ADR pin thereof, whichever operation mode the microprocessor is set to. The ADR signal is supplied to the mode setting circuit, thus electrically disconnecting the same from the one-chip microprocessor. Consequently, data other than the mode data can be written into the I/O pins.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: Disclosed is a non-volatile memory system which includes a first power means for providing a main power source; a read/write memory means for storing and retrieving data signals so long as power is provided; and second power means for coupling to the first power means and to the read/write memory means, the second power means including auxiliary power means for providing a second power source; the second power means further including controller means for continuously providing power to the read/write memory means from either the first power means or the auxiliary power means. In the preferred embodiment, the first power means is within a housing, said housing having a compartment for the receipt of a plug-in module, and the second power means and read/write memory means are contained within the plug-in module. Additionally, in the preferred embodiment, the memory means and the second power means exclusive of the second power source are comprised of a single integrated circuit.

Abstract: This circuit provides a minimally sized data transfer buffer interface between two central processing units for transferring data blocks of variable size. The circuit provides an indication to one CPU that the other CPU has received all the data words transmitted.

Abstract: A fuel control (23) for an aircraft engine (10) employs super contingency logic (76) in response to low rotor speed of a helicopter (130) engine failure (131) or entry into an avoid region of a flight regime following engine failure (133) to alter (161, 166-169) limits on the gas generator (30) of a free turbine gas engine (10), whereby following engine failure or in periods of extreme power need, risk of stressing an engine to its failure point is undertaken in favor of acquiring enough power to avoid a certain crash.

Abstract: A geographically distributed multiprocessor system is implemented by locating groups of processors at nodes which are interconnected by way of a transport network and which are connected by way of local lines to customer terminals and hosts. Each processor supports a plurality of processes which communicate with other processes in the same processor by way of internal links and with other processes in other processors by way of combinations of internal links and external communication links. Interface processes exchange data between the internal and external links. A process can initiate a call to any other process and define the communication parameters for exchanging data information by selecting the appropriate internal link and supplying the code defining the communication parameters to the selected internal link.

Abstract: The method uses digital data processing means and stored representations of a table of textual block identifiers for locating in a stored textual data base those textual blocks having the best match with a query. Textual block identifiers each provide an indication of a textual block in a stored data base which contains the corresponding word. The method comprises the following steps: A query word is received having representations of a plurality of words to be located in textual blocks in the stored data base. For each of a plurality of the query words, determine a corresponding set of equivalent words which are contained in the stored data base. Each set of equivalent words is equivalent to the corresponding query word. Each equivalent word has a corresponding group of textual block identifiers represented in the stored table.

Abstract: Herein disclosed is a job execution multiplicity controlling method, in which the used time periods of the central unit and the input/output device of at least one processor, respectively, are periodically measured for the respective jobs being executed in parallel in that processor, in which whether the present workload upon that processor is reasonable or not is judged in accordance with that measurement result, and in which a subsequent new job execution is started in that processor when that workload is lower.

Abstract: An arbiter cooperating with p.n processing units grouped into p levels each comprising n processing units. An elementary arbiter is assigned to each level, and a central arbiter attributes cyclically the priority to each level. The central arbiter comprises essentially a memory programmed for attributing a single priority to each level.