Patents Examined by Roy Potter
  • Patent number: 9982339
    Abstract: A mask comprises a mask substrate having a protruding section in an opening end surface of an opening, having an acute angle defined by ?1 and ?2 of no more than 43°, and having a height from a film-formation surface on the substrate to a tip section of the protruding section greater than the thickness of the film to be formed on the film-formation surface.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 29, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuya Okamoto, Takeshi Hirase, Tohru Senoo, Tohru Sonoda, Daichi Nishikawa, Mamoru Ishida
  • Patent number: 9978881
    Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
  • Patent number: 9978783
    Abstract: A semiconductor device includes first and second photo-electric conversion elements, each having a light-receiving surface, disposed adjacent to each other, each outputting a light current that is a current corresponding to an intensity of received light, a first filter disposed on the light-receiving surface of the first photo-electric conversion element, a second filter disposed on the light-receiving surface of the second photo-electric conversion element, and a third filter disposed on the light-receiving surface of the second photo-electric conversion element and being in contact with the second filter, one end of the second filter and one end of the third filter overlapping one end of the first filter at a vicinity of a boundary between the first photo-electric conversion element and the second photo-electric conversion element.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 22, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Patent number: 9978785
    Abstract: An image sensor may include: a substrate including a photoelectric conversion element; a first interlayer dielectric layer formed over the photoelectric conversion element; a channel layer including a first region and a second region, the first region being formed in an opening passing through the first interlayer dielectric layer, with a portion of the first region contacting the photoelectric conversion element, and the second region being formed over the first interlayer dielectric layer; a transfer transistor formed over the first region of the channel layer, the transfer transistor including a transfer gate which gapfills the opening; and a reset transistor including a reset gate formed over the second region of the channel layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventors: Pyong-Su Kwag, Ho-Ryeong Lee
  • Patent number: 9978840
    Abstract: In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 22, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 9978777
    Abstract: A TFT array panel of a display device includes a first substrate, a first electrode disposed on the first substrate, a first insulating layer including a first hole, the first insulating layer disposed on the first electrode, a second insulating layer disposed on the first insulating layer and including a second hole corresponding to the first hole, and a capping layer including a first inner portion, the capping layer disposed on an inner lateral surface forming the second hole, where an end portion of the first inner portion disposed in the second hole is separated from the first electrode.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae An Seo, Su Bin Bae, Yu-Gwang Jeong, Hyun Min Cho, Shin Il Choi, Jin Hwan Choi
  • Patent number: 9978649
    Abstract: A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing fins of first and second film stacks, sacrificial gates across and on the fins of the first and second film stacks, where the first and second film stacks include alternating first and second films, and where the first films extend through sidewall spacers on the sacrificial gates, selectively forming a first mask layer on the sidewall spacers and on the first films of the first film stack, depositing a first dopant layer on the substrate, heat-treating the substrate to diffuse dopants from the first dopant layer into the first films of the second film stack to form doped first films in the second film stack, and removing the first mask layer from the substrate. The processing steps may be repeated for the second film stack.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 22, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Steven P. Consiglio, Jeffrey Smith
  • Patent number: 9978727
    Abstract: A display apparatus including a light emitting diode part including a plurality of regularly arranged light emitting diodes, and a thin-film transistor (TFT) panel part including a plurality of TFTs configured to drive the light emitting diodes disposed on the TFT panel part. The light emitting diode part further includes a transparent substrate disposed on the light emitting diodes, and a phosphor layer disposed on the transparent substrate and configured to emit at least one of blue light, green light, and red light by converting at least a portion of a wavelength of light emitted from the light emitting diodes, in which a thickness of the transparent substrate is less than a thickness of the phosphor layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 22, 2018
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Young Hyun Kim, Jong Ik Lee
  • Patent number: 9972573
    Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 15, 2018
    Assignee: Invensas Corporation
    Inventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
  • Patent number: 9966464
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 8, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Kapil Kelkar, Timothy D. Henson, Ling Ma, Mary Bigglestone, Adam Amali, Hugo Burke, Robert Haase
  • Patent number: 9963342
    Abstract: A method for distinguishing carbon nanotubes comprising: providing a conductive substrate and applying an insulating layer on the conductive substrate; forming a carbon nanotube structure on a surface of the insulating layer, the carbon nanotube structure includes at least one carbon nanotube; placing the carbon nanotube structure under a scanning electron microscope, adjusting the scanning electron microscope with an accelerating voltage ranging from 5˜20 KV, a dwelling time ranging 6˜20 microseconds and a magnification ranging from 10000˜100000 times; taking photos of the carbon nanotube structure with the scanning electron microscope; and, obtaining a photo of the carbon nanotube structure, the photo shows the at least one carbon nanotube and a background.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 8, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Dong-Qi Li, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9960285
    Abstract: One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chung-Yen Chou, Po-ken Lin, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9960354
    Abstract: A method for making thin film transistor includes: providing a gate electrode and forming an insulating layer on the gate electrode; providing a carbon nanotube film comprising a plurality of metallic carbon nanotubes and a plurality of semiconducting carbon nanotubes; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope to take photo of the carbon nanotube film to distinguish the plurality of metallic carbon nanotubes and the plurality of semiconducting carbon nanotubes; removing the metallic carbon nanotubes, and forming a source electrode and a drain electrode on a surface of the semiconducting layer.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 1, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Dong-Qi Li, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9953950
    Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9954054
    Abstract: A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 24, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 9953865
    Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 9947649
    Abstract: A semiconductor structure including an electrostatic discharge (ESD) diode with an increased junction area and a vertical field effect transistor (FET) formed on a same substrate is provided. The ESD diode is formed by forming a first doped semiconductor segment merging bottom portions of a pair of semiconductor fins and then forming a second doped semiconductor segment having a conductivity type opposite to that of each of the first doped semiconductor segment and the pair of semiconductor fins. A U-shaped p-n junction is present between the second doped semiconductor segment and the first doped semiconductor segment and the second doped semiconductor segment and the pair of semiconductor fins.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 9944772
    Abstract: An organosiloxane represented by the following general formula; a curable silicone composition comprising: (A) an organopolysiloxane having at least two alkenyl groups in a molecule; (B) an organohydrogenpolysiloxane having at least two silicon atom-bonded hydrogen atoms in a molecule; (C) an adhesion promoter containing the organosiloxane; and (D) a catalyst for hydrosilylation reaction; and a semiconductor device in which a semiconductor element is encapsulated with a cured product of the composition. A novel organosiloxane, a curable silicone composition that contains the novel organosiloxane as an adhesion promoter and that forms a cured product having excellent adhesion to various base materials, and a semiconductor device that is formed by using the composition and that has excellent reliability are provided.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 17, 2018
    Assignee: DOW CORNING TORAY CO., LTD.
    Inventors: Tomohiro Iimura, Nohno Toda, Sawako Inagaki, Yusuke Miyamoto, Haruhiko Furukawa
  • Patent number: 9947742
    Abstract: A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 17, 2018
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Hye-mi Kim, Sun-hak Lee
  • Patent number: 9947671
    Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Youn Kim