Patents Examined by S. Jackson
  • Patent number: 5510948
    Abstract: A low voltage power supply and distribution center comprises a housing (12) having three internal compartments including: a high voltage compartment (17), a low voltage distribution compartment (19), and a transformer compartment (21). The housing (12) is designed for surface or recessed mounting on or in a wall or ceiling. For recessed mounting, with the housing (12) surrounded with 20 cm (8 inches) of insulation, the maximum surface temperature of the housing is less than C. The three compartments (17,19,21) are formed by a removable power tray (15) having a torodial transformer (132) mounted thereon. The low voltage compartment (19) comprises a fuse panel (150) for mounting a plurality of plug-in fuses (153) from which the low voltage power is distributed. The high voltage compartment (17) comprises a switch or a dimmer (131) in a high voltage line between the transformer (132) and the incoming high voltage line, or the dimmer or switch may be remotely installed on a wall.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: April 23, 1996
    Assignee: Q Tran, Inc.
    Inventors: Susan C. Tremaine, John M. Tremaine
  • Patent number: 5502610
    Abstract: A switching circuit has a pull-up FET and a pull-down FET coupled to a load circuit, each FET having a control terminal coupled to a current regulating circuit. The current regulating circuit provides a high predetermined current for a relatively short duration to the gates of the FETs to quickly turn on or turn off the FETs. After the short duration, a low quiescent current is applied to the gates to maintain the FETs in their present states. An inhibiting circuit, coupled between the pull-up FET and the pull-down FET, detects the states of the FETs and delays turn-on of one FET until the other FET has turned off. An overcurrent circuit monitors a current through a switching FET and turns off the FET after a predetermined time delay when an overcurrent condition is detected. The overcurrent circuit then turns on the FET after another predetermined time delay.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: March 26, 1996
    Assignee: Micrel, Inc.
    Inventor: Steve I. Chaney
  • Patent number: 5500782
    Abstract: A protector arrangement is disclosed having first and second protector terminals, a gas discharge tube, and a metal oxide varistor. The gas discharge tube is connected to the first and second protector terminals. The metal oxide varistor is connected to the first and second protector terminals so that the metal oxide varistor acts as a backup to the gas discharge tube and so that the first and second protector terminals are automatically shorted in response to a thermal overload condition. The protector arrangement may be mounted in a weathertight housing.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: March 19, 1996
    Assignee: Joslyn Electronic Systems Corporation
    Inventors: Hans-Wolfgang Oertel, David L. Martin
  • Patent number: 5495383
    Abstract: A circuit for protecting a semiconductor circuit or a telephone communication line from a lightning surge or overvoltage or overcurrent condition. The circuit incorporates a two-terminal surge absorbing device arranged in parallel with the circuit or line to be protected, a thermistor having a high positive temperature coefficient, arranged in series to the circuit or line, between the electric source and the surge absorbing means, and a resistor connected in series with the circuit or line.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: February 27, 1996
    Assignee: Mitsubishi Mining & Cement Co., Ltd.
    Inventors: Naruo Yoshioka, Takaaki Ito, Takashi Kurihara
  • Patent number: 5495384
    Abstract: The present invention provides an arrangement for automatic selective circuit interruption in response to detection of a fault in a multi-phase distribution system feeding a plurality of network branches. The arrangement includes a plurality of line monitoring devices which are programmed to alarm a control station in response to detection of a fault in the system. In response to being alarmed by one or more line monitoring devices, the control station activates a specialized signal generator which produces a specialized signal along one of the lines of the multi-phase system. Each line monitoring device is co-located with and communicatively coupled to a circuit interrupter which, when actuated, prevents the flow of current in lines of the system positioned downstream from the actuated circuit interrupter. Each line monitoring device automatically actuates the coupled circuit interrupter within a prescribed period of time following detection of the specialized signal.
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Square D Company
    Inventors: Lee D. Wallis, Robert A. Kennedy
  • Patent number: 5485343
    Abstract: A digital circuit interrupter utilizing current transformers for operating power is provided with a re-chargeable battery to power-up the trip unit as well as to power the display after an overcurrent trip occurrence to enable an operator to determine both the magnitude as well as the cause of the overcurrent condition.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: January 16, 1996
    Assignee: General Electric Company
    Inventors: Esteban Santos, Hanns P. Sailer, Paul H. Singer, Indrajit Purkayastha
  • Patent number: 5477407
    Abstract: An input protection circuit includes a conductor pattern extending from a first end connected to an input pad to a second end connected to an integrated circuit, first and second, mutually separated ground patterns disposed at both sides of the conductor pattern with a separation therefrom, a first gate pattern provided on a gap between the conductor pattern and the first ground pattern, and a second gate pattern provided on a gap between the conductor pattern and the second ground pattern, wherein the conductor pattern, the first ground pattern and the first gate pattern form a first transistor extending continuously from the first end to the second end of the conductor pattern at a first side of the conductor pattern, and wherein the conductor pattern, the second ground pattern and the second gate pattern form a second transistor extending continuously from the first end to the second end of the conductor pattern at a second side of the conductor pattern.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: December 19, 1995
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Isamu Kobayashi, Yasunori Murase
  • Patent number: 5477408
    Abstract: The system includes a blocking counter which is set to 255 quarter cycles and the output contacts of the protective relay are blocked for five quarter cycles if the first order difference between two successive quarter-cycle samples of current is above a selected threshold, referred to as the last previous and the first samples. The first order difference between the first and the next successive (second) samples is compared against a second threshold and the instantaneous value of the current sample is compared against the second threshold. If both comparisons are above the second threshold, then the output contacts are unblocked. If not, such that a constant DC A/D converter output or an A/D spike is indicated, then the outputs remain blocked for the full five quarter cycles, which is sufficient time to permit the A/D spike to disappear and to recognize a constant DC output from the A/D converter.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: December 19, 1995
    Assignee: Schweitzer Engineering Labs, Inc.
    Inventors: Edmund O. Schweitzer, III, Timothy P. Tibbals
  • Patent number: 5477413
    Abstract: An ESD protection structure for p-well technology using nMOS FETs that prevents the lock-on condition normally occurring after one FET of a multi finger structure snaps back. The multifinger structure is contained in a main p-well and channels ESDs of a first polarity from the contact pad to a metal conduit. A resistance is provided between the main p-well and the conduit. Further, the circuit channeling ESDs of a polarity opposite to the first polarity is contained in a second p-well that is distinct from the main p-well. An ESD event causes one of the fingers to snap back. Resulting drain current through that finger generates electron hole pairs in the main p-well by impact ionization. Thus generated holes, traveling to the conduit through the resistance, raise the voltage of the main p-well, and therefore shift the i-v characteristic curves of all the FETs to a point where they no longer exhibit a knee.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: December 19, 1995
    Assignee: Cypress Semiconductor Corp.
    Inventor: Jeffrey T. Watt
  • Patent number: 5473497
    Abstract: A device for measuring energy delivered by a motor to a load is adapted to be connected to the motor which is coupled to the load and connected to a power source through first and second power supply lines. The device includes a line voltage sensing circuit for sensing the voltage across the power supply lines, a line current sensing circuit for sensing the current flowing through the motor and a pulse width modulator which modulates the sensed voltage to produce a pulse width modulated first electrical signal. The device also includes a first switch, responsive to the pulse width modulated first electrical signal which modulates an output of the line current sensing circuit to produce a power waveform and an integrator which integrates the power waveform to produce an output signal indicative of the energy delivered by the motor to the load.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: December 5, 1995
    Assignee: Franklin Electric Co., Inc.
    Inventor: James A. Beatty
  • Patent number: 5469320
    Abstract: An efficient fan drive circuit to drive a variable fan used in a power supply of a personal computer system. The fan drive circuit uses a diode to establish the minimum fan speed during operation in the normal temperature range. The bleeder resistor normally coupled between the fan and a negative output voltage is removed and replaced with a current source. The current source also serves to shut down the power supply if the fan is not operating properly or is not installed. A shut down circuit remains to shut down the power supply when excessive temperature occurs, or when the current source detects that the fan is malfunctioning or not installed.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: November 21, 1995
    Assignee: Compaq Computer Corp.
    Inventors: Richard E. Walker, Hai N. Nguyen
  • Patent number: 5461532
    Abstract: A pulse transformer circuit which comprises a transformer core having a plurality of individual primary windings and a secondary winding, a plurality of preferably single turn primary circuits, each primary circuit coupled to a different one of the primary windings. Each primary circuit comprises a switch in series with the primary winding, a capacitor coupled across the primary winding and the switch and a voltage source coupled across the capacitor. A load circuit is coupled across said secondary winding. The switch is a semiconductor device having a control electrode and a current carrying path coupled to the primary winding and controlled by the control electrode. A clamp circuit can be coupled to the load circuit to minimize voltage overshoot in the secondary winding.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: October 24, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Gary B. Eastman
  • Patent number: 5457593
    Abstract: A protector block assembly for coupling a plurality of surge protectors to multi-line telecommunications cables includes a multi-layer printed circuit, to which has been mounted at least two cable connectors, and a protector block having a plurality of sockets for receiving standard surge protectors. A plurality of pins electrically and physically connects the multi-layer printed circuit board to the sockets on the protector block in a manner that a unique signal path exists between each lead in each connector and one of the sockets on the printed circuit board. The multi-layer printed circuit board includes traces on multiple layers that have a width and a copper content sufficient to carry current surges without breaking down.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: October 10, 1995
    Assignee: ACT Communications, Inc.
    Inventors: James A. Glaser, Ronald W. Glaser
  • Patent number: 5455734
    Abstract: An insert device employing electronics is non-intrusively disposed between an electronic mechanism's pins and female connector in order to provide the mechanism with electronic functional capabilities. The insert device is of a shape, size, and character such that normal mating engagement between the mechanism's pins and connector is unaffected.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: October 3, 1995
    Assignee: TRW Inc.
    Inventors: Kevin G. Foreman, Willie C. Kiser, Paul J. Miller
  • Patent number: 5452171
    Abstract: An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: September 19, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Larry S. Metz, Gordon W. Motley
  • Patent number: 5450266
    Abstract: A fault current limiter for use in alternating current transmission utilizes a (high temperature) superconductor body. If the current density through the body exceeds a critical value, the superconductor becomes a resistor; the fault current limiter makes use of this principle. In order to enable the critical current density to be selected from within a range of different values, the superconductor is immersed in a volume of cryogenic liquid, e.g. liquid nitrogen, in a vessel provided with a closure having an outlet communicating with a duct in which is disposed a manually adjustable back pressure regulator. The back pressure regulator enables the pressure in the ullage space of the vessel to be set at a chosen value, usually below atmospheric pressure. The liquid nitrogen is stored in the vessel at its boiling point which depends on the pressure in the ullage space. Accordingly, the temperature of the liquid nitrogen can be set by the regulator.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: September 12, 1995
    Assignee: The BOC Group plc
    Inventor: Neil A. Downie
  • Patent number: 5450268
    Abstract: A method and apparatus provides for a measurement technique which approximates the true rms value of a current waveform. The technique involves converting the current waveform to a voltage by rectification and determining the peak value and the average value of the resultant voltage. A summing circuit combines the two values at a predetermined ratio to create a DC voltage that is approximately equal to the rms value of the input currents. The DC voltage output is suitable for a wide range of applications. A combination of the approximation circuit with a time integrating circuit and a level detecting circuit produces a low cost solid state overload relay in a preferred embodiment of the invention. Other uses include metering and use as a current feedback control signal for controlling PWM inverters and the like.
    Type: Grant
    Filed: August 11, 1993
    Date of Patent: September 12, 1995
    Assignee: Square D Company
    Inventors: Timothy B. Phillips, Antoine D. Stentz
  • Patent number: 5450267
    Abstract: An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: September 12, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Carlos H. Diaz, Charvaka Duvvury, Sung-Mo Kang
  • Patent number: 5450269
    Abstract: A grounding arrangement for a protector includes an arrester device having two conducting points for connecting to inlet prongs and a grounding point having a protruding rod for connecting to a grounding prong, an arrester holder for receiving the arrester device and having two longitudinal extension portions for connecting with the two conducting points, and a tin bit provided for electrically connecting the holder and the grounding point of the arrester device and isolating the holder and two conducting point of the arrester device.
    Type: Grant
    Filed: September 17, 1993
    Date of Patent: September 12, 1995
    Inventor: Kin L. Hsieh
  • Patent number: 5448442
    Abstract: A motor control unit for protecting a motor against overload, short circuit and ground fault currents. The unit monitors the currents in each phase of the motor to provide values representative of each phase current. The unit also includes a contactor for opening and closing each phase, wherein the unit controls the contactor based upon the values representative of the phase currents. The contactor is opened where the phase currents exceed limits which indicate that either an overload, short circuit or ground fault situation exists at the motor. A magnetic trip circuit breaker can also be provided to operate in cooperation with the unit to provide instantaneous trip protection for current levels which are relatively high in relation to those for which the contactor is rated.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: September 5, 1995
    Assignee: Siemens Energy & Automation, Inc.
    Inventor: Samir F. Farag